Array substrates and methods for manufacturing thereof and display screens

US10985195B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10985195-B2
Application numberUS-201916513734-A
CountryUS
Kind codeB2
Filing dateJul 17, 2019
Priority dateNov 30, 2017
Publication dateApr 20, 2021
Grant dateApr 20, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to an array substrate. The array substrate includes an active area; and a non-active area located outside the active area. The non-active area includes a flexible substrate having a surface provided with a number of grooves, and a peripheral metal wiring located in the number of grooves.

First claim

Opening claim text (preview).

The invention claimed is: 1. An array substrate, comprising: an active area; and a non-active area located outside the active area; wherein the non-active area comprises: a flexible substrate having a surface, wherein the flexible substrate is provided with a plurality of grooves, and a peripheral metal wiring being located in the plurality of grooves, wherein: a width of the peripheral metal wiring is less than a width of the groove, the peripheral metal wiring is located at an intermediate position of the groove, the non-active area further comprises a buffer strip formed in the groove, and the buffer strip fills between both sides of the peripheral metal wiring and the groove, along a width direction, wherein the non-active area further comprises a stress buffer layer formed between bottom walls of the grooves and the peripheral metal wiring, wherein the stress buffer layer is provided with a plurality of through holes. 2. The array substrate of claim 1 , wherein depths of the plurality of grooves are different from each other. 3. The array substrate of claim 1 , wherein the non-active area further comprises an encapsulation layer formed on a surface of the flexible substrate proximate to the peripheral metal wiring. 4. The array substrate of claim 1 , wherein the flexible substrate comprises a flexible substrate main layer, and a flexible substrate surface layer is formed on a surface of the flexible substrate main layer adjacent to the peripheral metal wiring. 5. The array substrate of claim 4 , wherein the flexible substrate main layer comprises at least one flexible substrate layer, and the flexible substrate surface layer comprises at least one flexible substrate layer. 6. The array substrate of claim 4 , wherein the flexible substrate surface layer is a patterned flexible substrate surface layer; and hollow regions of the flexible substrate surface layer and the flexible substrate main layer form the grooves. 7. The array substrate of claim 4 , wherein a thickness of the flexible substrate surface layer is equal to a depth of the groove. 8. The array substrate of claim 1 , wherein the plurality of grooves is arranged in a grid shape. 9. A display screen, comprising the array substrate of claim 1 . 10. The array substrate of claim 1 , wherein the flexible substrate comprises a plurality of stacked flexible substrate layers. 11. The array substrate of claim 1 , wherein a cross section of each of the plurality of grooves comprises a trapezoid. 12. A method for manufacturing an array substrate comprising an active area and a non-active area, comprising manufacturing the non-active area of the array substrate, wherein the manufacturing the non-active area of the array substrate comprises: providing a flexible substrate; forming a plurality of grooves on a surface of the flexible substrate; forming a stress buffer layer on bottom walls of the plurality of grooves; forming a plurality of through holes in the stress buffer layer within the grooves; forming a peripheral metal wiring in the plurality of grooves, and forming a buffer strip on both sides of the peripheral metal wiring in the plurality of grooves. 13. The method of claim 12 , wherein the forming the plurality of grooves on the surface of the flexible substrate comprises: providing a flexible substrate main layer; and forming a patterned flexible substrate surface layer on the flexible substrate main layer, hollow regions of the flexible substrate surface layer and the flexible substrate main layer forming the grooves. 14. The method of claim 13 , wherein the forming the patterned flexible substrate surface layer on the flexible substrate main layer comprises: forming the patterned flexible substrate surface layer on the flexible substrate main layer by means of a mask.

Assignees

Inventors

Classifications

  • characterised by materials, geometry or structure of the substrates · CPC title

  • comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

  • comprising manufacture, treatment or coating of substrates · CPC title

  • of multiple TFTs · CPC title

  • H10D86/443Primary

    adapted for preventing breakage, peeling or short circuiting · CPC title

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Frequently asked questions

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What does patent US10985195B2 cover?
The present disclosure relates to an array substrate. The array substrate includes an active area; and a non-active area located outside the active area. The non-active area includes a flexible substrate having a surface provided with a number of grooves, and a peripheral metal wiring located in the number of grooves.
Who is the assignee on this patent?
Kunshan Govisionox Optoelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/443. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 20 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).