Interposer-based damping resistor

Patent metadata

Field	Value
Publication number	US-10985097-B2
Application number	US-201816048630-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Mar 30, 2012
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

First claim

What is claimed is:

1. An apparatus, comprising:
an interposer adapted to have a first semiconductor chip mounted thereon, the interposer having an onboard resistor adapted to dampen a capacitive network, the capacitive network having at least one capacitor positioned off the interposer and the first semiconductor chip; and
an intermediate power network, a ground, and a grounded overlap conductor, the offboard capacitor being coupled between the intermediate power network and the ground.

2. The apparatus of claim 1 , comprising a circuit board, the interposer and the at least one capacitor being coupled to the circuit board.

3. The apparatus of claim 1 , wherein the onboard resistor comprises a conductor line coupled to a first through-silicon-via.

4. The apparatus of claim 3 , wherein the onboard resistor comprises a second through-silicon-via coupled to the conductor line, the first and second through-silicon-vias and the conductor line being connected in series.

5. The apparatus of claim 1 , comprising the first semiconductor chip coupled to the interposer.

6. The apparatus of claim 1 , comprising a second semiconductor chip coupled to the interposer.

7. An apparatus, comprising:
a circuit board;
an interposer adapted to have a first semiconductor chip mounted thereon, the interposer having an onboard resistor adapted to dampen a capacitive network, the capacitive network having at least one capacitor positioned off the interposer and the first semiconductor chip, the interposer and the at least one capacitor being coupled to the circuit board; and
an intermediate power network, a ground, and a grounded overlap conductor, the offboard capacitor being coupled between the intermediate power network and the ground.

8. The apparatus of claim 7 , wherein the onboard resistor comprises a conductor line coupled to a first through-silicon-via.

9. The apparatus of claim 8 , wherein the onboard resistor comprises a second through-silicon-via coupled to the conductor line, the first and second through-silicon-vias and the conductor line being connected in series.

10. The apparatus of claim 7 , comprising the first semiconductor chip coupled to the interposer.

11. The apparatus of claim 7 , comprising a second semiconductor chip coupled to the interposer.

12. An method, comprising the steps of:
providing an interposer adapted to have a first semiconductor chip mounted thereon, the interposer having an onboard resistor adapted to dampen a capacitive network, the capacitive network having at least one capacitor positioned off the interposer and the first semiconductor chip; and
providing an intermediate power network, a ground, and a grounded overlap conductor, the offboard capacitor being coupled between the intermediate power network and the ground.

13. The method of claim 12 , comprising providing a circuit board, the interposer and the at least one capacitor being coupled to the circuit board.

14. The method of claim 12 , wherein the onboard resistor comprises a conductor line coupled to a first through-silicon-via.

15. The method of claim 14 , wherein the onboard resistor comprises a second through-silicon-via coupled to the conductor line, the first and second through-silicon-vias and the conductor line being connected in series.

16. The method of claim 12 , wherein the first semiconductor chip is coupled to the interposer.

17. The method of claim 12 , comprising providing a second semiconductor chip coupled to the interposer.

Assignees

• Ati Technologies Ulc
• Advanced Micro Devices Inc

Inventors

• Guo Fei
• Zhu Feng
• Din Julius
• Kashem Anwar
• Yeung Sally

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• Y10T29/4913

  Assembling to base an electrical component, e.g., capacitor, etc. · CPC title