Method for training multichannel data receiver timing

Patent metadata

Field	Value
Publication number	US-10983944-B2
Application number	US-201916251066-A
Country	US
Kind code	B2
Filing date	Jan 17, 2019
Priority date	Jan 17, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

First claim

What is claimed is:

1. An apparatus, comprising:
a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus, wherein the first device includes:
a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal, including by:
determining, using a first set of sampling operations, a first timing relationship, including a plurality of data skew values, wherein individual ones of the plurality of data skew values are determined based on comparisons of respective data bit signals of the plurality of data bit signals to the data strobe signal; and
determining, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal;

wherein the control circuit is configured, during an operational phase, to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

2. The apparatus of claim 1 , wherein the control circuit is further configured to:
during the training phase, redetermine, using the delays based on the first and second timing relationships for a third set of sampling operations, the first timing relationship of the plurality of data bit signals relative to the data strobe signal; and
during the operational phase, use delays based on the redetermined first timing relationship and the second timing relationship to sample data from the second device on the data bus.

3. The apparatus of claim 1 , wherein the control circuit is further configured to perform the first and second sets of sampling operations by requesting a known data pattern from the second device.

4. The apparatus of claim 3 , wherein the control circuit is further configured to determine the delays based on the first and second timing relationships by comparing the known data pattern to data values received during the first and second sets of sampling operations.

5. The apparatus of claim 1 , wherein to determine the second timing relationship, the control circuit is further configured to perform the second set of sampling operations using the plurality of data skew values.

6. The apparatus of claim 1 , wherein the control circuit is further configured to select a maximum data skew value from the plurality of data skew values and set a strobe delay on the data strobe signal based on the maximum data skew value.

7. The apparatus of claim 1 , wherein the control circuit is further configured to select a maximum data skew value from the plurality of data skew values and set a respective delay on individual data bit signals of the plurality of data bit signals based on a difference between the maximum data skew value and a corresponding data skew value.

8. A method comprising:
performing, by a first device, a training operation to determine relative timing between a clock signal, a plurality of data bit signals on a data bus, and a data strobe signal used to communicate with a second device, wherein the training operation includes:
generating a first data set from a first set of sampling operations;
determining, by the first device, a first timing relationship, including a plurality of data skew values, wherein individual ones of the plurality of data skew values are determined by comparing respective data bit signals of the plurality of data bit signals to the data strobe signal;
generating a second data set from a second set of sampling operations; and
determining, by the first device, based on the second data set, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal; and

using, by the first device during an operational phase, delays based on the first and second timing relationships to sample data from the second device on the data bus.

9. The method of claim 8 , wherein the training operation further comprises:
generating, by the first device, a third data set from a third set of sampling operations that utilize the delays based on the first and second timing relationships; and
using the third data set, redetermining, by the first device, the first timing relationship of the data bus relative to the data strobe signal; and
during the operational phase, using delays based on the redetermined first timing relationship and the second timing relationship to sample data from the second device on the data bus.

10. The method of claim 8 , wherein generating the second data set from the second set of sampling operations includes performing the second set of sampling operations using the plurality of data skew values.

11. The method of claim 8 , further comprising:
performing the first set of sampling operations by requesting a known data pattern from the second device; and
generating the first data set by sampling data sent by the second device, via the data bus, while delaying the data strobe signal for a different amount of time for each data sample.

12. The method of claim 11 , further comprising:
performing the second set of sampling operations by requesting the known data pattern from the second device; and
generating the second data set by sampling data sent by the second device while delaying the data strobe signal and the plurality of data bit signals for a different amount of time for each data sample.

13. The method of claim 11 , wherein determining the first timing relationship comprises identifying, by the first device, data values in the first data set that equal the known data pattern or a second value that is based on the known data pattern.

14. The method of claim 13 , wherein determining the first timing relationship comprises identifying, by the first device, a longest consecutive series of data values in the first data set that equal the known data pattern or the second value.

15. A non-transitory computer-readable medium having instructions stored thereon that are executable by a computer system to perform operations comprising:
performing a training operation on a data receiver circuit to determine relative timing between a clock signal, a plurality of data bit signals on a data bus, and a data strobe signal used to communicate with a different device, wherein to perform the training operation the operations further include:
determining a first timing relationship between the plurality of data bit signals and the data strobe signal based on a first set of results of a first set of sampling operations;
setting a data bus delay and a data strobe delay based on the first set of results; and
using the data bus delay and data strobe delay, determining a second timing relationship of both the plurality of data bit signals and the data strobe signal relative to the clock signal based on a second set of results of a second set of sampling operations;
adjusting the data bus delay and the data strobe delay based on the second set of results; and
using the data bus delay and the data strobe delay, re-evaluating the first timing relationship between the plurality of data bit signals and the data strobe signal based on a third set of results from a third set of sampling operations;
setting a revised data bus delay and a revised data strobe delay based on the second timing relationships and the re-evaluated first timing relationship; and

subsequent to an end of the training operation, using the revised data bus delay and the revised data strobe delay to sample

Assignees

• Oracle Int Corp

Inventors

• Jamadagni Navaneeth P
• Jang Ji Eun
• Yakovlev Anatoly
• Lee Vincent
• Shu Guanghua
• Semmelmeyer Mark

Classifications

• G06F13/4217

  with synchronous protocol · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title