System and method for reliable high-speed data transfer in multiple data rate nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9811273-B1
Application number	US-201414580833-A
Country	US
Kind code	B1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.

First claim

What is claimed is:

1. A method for reliable high speed data transfer in multiple data rate nonvolatile memory, the method comprising:
establishing a memory controller and a nonvolatile memory having a communication link therebetween;
establishing a range of delay values representing relative delay between a plurality of data signals and a data strobe signal for data transmission from the memory controller to the nonvolatile memory through the communication link;
selectively establishing a training portion in the nonvolatile memory defined based on a smallest erasable unit of the nonvolatile memory;
providing at least one known data pattern;
executing the memory controller to:
sequentially write the known data pattern to different segments of the training portion of the nonvolatile memory, the known data pattern being written repetitively in the segments of the training portion and relative to the data strobe signal at different delay values within the established range for each written segment;
sequentially read each of the segments to compare the data pattern read with the known data pattern and thereby identify each correctly written segment, a first of the correctly written segments defining a leading edge of alignment between data and data strobe signals, a last of the correctly written segments defining a trailing edge of alignment between data and data strobe signals; and
establish an optimal delay value as a mean delay value between the delay values of the leading and trailing edge alignment, subsequent write operations to the nonvolatile memory being executed based on the optimal delay value.

2. The method as recited in claim 1 , wherein the established range of delay values are a step-wise range of discrete values, each delay value of the established range being associated with a corresponding one of the segments of the training portion.

3. The method as recited in claim 1 , wherein selectively establishing a training portion further includes evaluations of blocks being unused, blocks being free of bad sectors, and wear leveling requirements of the nonvolatile memory.

4. The method as recited in claim 1 , wherein an individual optimal delay value is established for each of the plurality of data signals relative to the data strobe signal.

5. The method as recited in claim 1 , further comprising:
encoding the known data pattern with an error correcting code (ECC) before being written to the training portion, and
using the ECC to restore bit errors of data read prior to comparison with the known data pattern.

6. The method as recited in claim 1 , wherein the segments of the training portion are of equal memory capacity.

7. A method for reliable high speed data transfer in multiple data rate nonvolatile memory, the method comprising:
establishing a memory controller and a nonvolatile memory having a communication link therebetween;
establishing a range of delay values representing relative delay between a plurality of data signals and a data strobe signal for data transmission from the memory controller to the nonvolatile memory through the communication link;
selectively establishing a training portion in the nonvolatile memory;
providing a known data pattern;
writing the known data pattern into the training portion of the nonvolatile memory at a first data rate;
repetitively reading the stored data pattern from the training portion of the nonvolatile memory as a plurality of data signals in conjunction with a data strobe signal, each reading at a sequentially different delay value within the established range, the readings being at a second data rate greater than the first data rate;
sequentially comparing the data patterns read from the training portion with the known data pattern to identify each correct reading; and,
responsive to the sequential comparisons, determining an optimum delay value that aligns rising and falling edges of the data strobe signal centrally between rising and falling edges of the data signals, subsequent read operations from the nonvolatile memory being executed at the second data rate based on the optimal delay value.

8. The method as recited in claim 7 , wherein selectively establishing a training portion includes evaluations of blocks being unused, blocks being free of bad sectors, and wear leveling requirements of the nonvolatile memory.

9. The method as recited in claim 7 , wherein the known data pattern is a pseudo-random sequence generated by a pseudo random pattern generator (PRPG).

10. The method as recited in claim 7 , wherein the first data rate is a Single Data Rate (SDR) keyed once per clock cycle.

11. The method as recited in claim 10 , wherein the second data rate is a Double Data Rate (DDR) keyed twice per clock cycle.

12. The method as recited in claim 7 , further comprising:
encoding the known data pattern with an error correcting code (ECC) before writing to the training portion, and
using the ECC to correct for bit-flips in data read from the training portion before comparing the read data pattern read with the known data pattern.

13. A system for reliable high speed data transfer in multiple data rate nonvolatile memory, the system comprising:
a memory controller including:
a timing generator establishing a data strobe signal output during write operations,
a plurality of delay circuits operable to selectively delay a received data strobe signal and a plurality of data signals output from the memory controller, and
a training module; and

a nonvolatile memory coupled to the memory controller by a data strobe signal line and a plurality of data signal lines for bidirectional transmission therebetween;
the training module of the memory controller being configured to:
(a) establish a range of delay values for respective use with the plurality of delay circuits to selectively delay the data strobe signal relative to data signals during a read training process,
(b) write a first known data pattern into a page of a training portion of the nonvolatile memory in a low speed mode,
(c) repeatedly read the page in a high speed mode while sequentially incrementing a delay value within the established range for each successive read operation to thereby sweep a delay of the data strobe signal through at least a portion of the range of delay values,
(d) compare the first known data pattern with data read during each successive read operation to identify each correct reading, a first of the correct readings defining a relative leading edge alignment, a last of the correct readings defining a relative trailing edge alignment, and
(e) determine an optimum read delay value of the data strobe signal relative to the data signals as a mean delay value between delay values of the leading and trailing edge alignment, subsequent read operations to the nonvolatile memory being executed based on the optimal read delay value.

14. The system for reliable high speed data transfer in multiple data rate nonvolatile memory as recited in claim 13 , where the training module is further configured to:
(f) repeatedly write a second known data pattern to sequential sectors of the training portion in a high speed mode while, for each write operation, sequentially incrementing a delay value and delaying, relative to the data strobe signal, the data signals providing the second known data pattern by the incremented delay value for each successive write operation, (g) sequentially read the sectors in a high speed mode at the optimum read delay value for the data strobe signal output from the nonvolatile memory, to thereby identify each sector correctly written with the second known data

Assignees

• Cadence Design Systems Inc

Inventors

• Brahmadathan Sandeep

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2206/1014

  One time programmable [OTP] memory, e.g. PROM, WORM · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title