Power diode and method of manufacturing a power diode

US10978596B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10978596-B2
Application numberUS-201816104799-A
CountryUS
Kind codeB2
Filing dateAug 17, 2018
Priority dateAug 18, 2017
Publication dateApr 13, 2021
Grant dateApr 13, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of processing a power diode, the method comprising: creating an anode region and a drift region in a semiconductor body; and forming each of an anode contact zone and an anode damage zone in the anode region, wherein the anode contact zone extends to a surface of the semiconductor body, wherein the anode damage zone is immediately beneath the anode contact zone, wherein the anode damage zone has a comparatively higher defect concentration and a comparatively lower dopant concentration than the anode contact zone, wherein forming the anode contact zone and the anode damage zone comprises an ion implantation step that uses one implantation energy to provide the dopants of the anode contact zone and the anode damage zone, wherein performing the ion implantation step comprises either: an uninterrupted implantation processing step that is carried out with non-variation of implantation energy, non-variation of implantation dose and with non-variation of implantation ions; or two or more uninterrupted implantation shots that are carried out each with non-variation of the implantation energy, with non-variation of the implantation dose and with non-variation of the implantation ions. 2. The method of claim 1 , wherein the ion implantation processing step comprises implanting heavy ions with a mass exceeding that of the 12/6 Carbon-nucleus or the 28/14 Silicium-nucleus. 3. The method of claim 1 , wherein the ion implantation processing step comprises implanting boron difluoride ions. 4. The method of claim 1 , wherein the ion implantation processing step is carried out with a beamline-implantation-device. 5. The method of claim 1 , wherein the ion implantation processing step is carried out with an implantation energy of less than 20 KeV. 6. The method of claim 1 , wherein the ion implantation processing step is carried out with an implantation dose of at least 2*10 13 cm −2 . 7. The method of claim 1 , wherein the ion implantation processing step is carried out such that a mean distance of the implanted ions, measured from a surface of the semiconductor body that has been penetrated by the implanted ions, is less than 100 nm. 8. The method of claim 1 , further comprising: after carrying out the ion implantation processing step, performing a temperature annealing processing step carried out at a temperature less than 450° C., wherein defects caused by the implanted ions are only partially annealed. 9. The method of claim 1 , wherein creating the anode region comprises at least one of an implantation processing step and a diffusion processing step. 10. The method of claim 1 , further comprising: before carrying out the ion implantation processing step, carrying out a first implantation processing step for forming an anode field stop zone within the anode region, the anode field stop zone being arranged deeper within the anode region than each of the anode contact zone and the anode damage zone. 11. The method of claim 10 , wherein the anode field stop zone is spatially displaced from the anode damage zone by at least 250 nm along a vertical direction. 12. The method of claim 10 , wherein implantation particles introduced in the anode region by means of the first implantation processing step are subjected to a temperature annealing processing step so as to anneal defects caused by the implantation particles. 13. The method of claim 1 , wherein the anode damage zone is configured to reduce at least one of a lifetime and a mobility of charge carriers present within the anode damage zone. 14. The method of claim 1 , further comprising: after the ion implantation processing step, providing an anode metallization on top of the anode region. 15. The method of claim 1 , wherein a maximum depth of the anode damage zone is no greater than 75 nm from the surface of the semiconductor body.

Assignees

Inventors

Classifications

  • of a molecular ion, e.g. decaborane · CPC title

  • into Group IV semiconductors · CPC title

  • of electrically active species · CPC title

  • H10D8/00Primary

    Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

  • into semiconductor materials, e.g. for doping · CPC title

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Frequently asked questions

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What does patent US10978596B2 cover?
A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H10D8/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 13 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).