Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry

Patent metadata

Field	Value
Publication number	US-10978554-B2
Application number	US-201916568504-A
Country	US
Kind code	B2
Filing date	Sep 12, 2019
Priority date	Jun 28, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material. Etching is conducted completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching is conducted into said conductive material. The covering material that is against the individual first sidewalls masks the individual first sidewalls from being etched during said etchings. Structure that may be independent of method is disclosed.

First claim

The invention claimed is:

1. An elevationally-elongated conductive structure of integrated circuitry, comprising:
conductive material electrically coupled to and extending upwardly relative to a lower node, the conductive material comprising an uppermost portion, a lower portion directly below the uppermost portion, and a lowest portion directly below the lower portion; the uppermost portion, the lower portion, and the lowest portion respectively having opposing first and second sidewalls in a same vertical cross-section;
the uppermost-portion first sidewall being laterally-between the lowest-portion first and second sidewalls, the uppermost-portion second sidewall being laterally-outward beyond the lowest-portion first and second sidewalls; the lower-portion first sidewall being laterally-between the lowest-portion first and second sidewalls, the lower-portion second sidewall being laterally-between the uppermost-portion first and second sidewalls; the lower-portion first sidewall being continuous with the uppermost-portion first sidewall; the lowest-portion first sidewall being laterally-outward beyond the uppermost-portion first sidewall and the lower-portion first sidewall, the lowest-portion second sidewall being laterally-between the uppermost-portion first and second sidewalls; and
covering material laterally over all of the uppermost-portion first and second sidewalls, the lower portion comprising a vertically-elongated and upwardly-open void space therein, the covering material extending into the void space, the void space comprising opposing conductive sidewalls in the vertical cross-section, the covering material:
being laterally over each of the opposing conductive sidewalls of the void space;
being laterally over an uppermost part of the lower-portion first sidewall above the opposing conductive sidewalls of the void space;
being laterally over the uppermost-portion first sidewall above the uppermost part of the lower-portion first sidewall; and
not being laterally over a lowermost part of the lower-portion first sidewall.

2. The structure of claim 1 wherein the covering material is directly against the conductive material of the uppermost-portion first sidewall.

3. The structure of claim 1 wherein the covering material comprises a composition different from that of the conductive material of the uppermost-portion first sidewall.

4. The structure of claim 1 wherein the covering material is insulative.

5. The structure of claim 1 wherein the covering material is not insulative.

6. The structure of claim 5 wherein the covering material comprises a composition different from that of the conductive material of the uppermost-portion first sidewall.

7. The structure of claim 1 wherein the covering material has a maximum thickness no greater than 100 Angstroms.

8. The structure of claim 1 as part of a memory cell.

9. The structure of claim 8 directly electrically coupled to a capacitor.

10. The structure of claim 8 directly electrically coupled to a capacitor.

11. The structure of claim 1 as part of a DRAM cell.

12. The structure of claim 1 wherein the lowest portion is thicker than the lower portion.

13. The structure of claim 1 wherein the lower portion is thicker than the uppermost portion.

14. The structure of claim 1 wherein,
the lowest portion is thicker than the lower portion; and
the lower portion is thicker than the uppermost portion.

15. The structure of claim 1 wherein the covering material completely fills the void space.

16. The structure of claim 1 wherein the covering material is directly above the void space.

17. The structure of claim 1 wherein the covering material completely fills the void space and is directly above the void space.

18. The structure of claim 1 wherein the void space is narrowest in the vertical cross-section at its bottom.

19. An elevationally-elongated conductive structure of integrated circuitry, comprising:
conductive material electrically coupled to and extending upwardly relative to a lower node, the conductive material comprising an uppermost portion, a lower portion directly below the uppermost portion, and a lowest portion directly below the lower portion; the uppermost portion, the lower portion, and the lowest portion respectively having opposing first and second sidewalls in a same vertical cross-section;
the uppermost-portion first sidewall being laterally-between the lowest-portion first and second sidewalls, the uppermost-portion second sidewall being laterally-outward beyond the lowest-portion first and second sidewalls; the lower-portion first sidewall being laterally-between the lowest-portion first and second sidewalls, the lower-portion second sidewall being laterally-between the uppermost-portion first and second sidewalls; the lower-portion first sidewall being discontinuous with the uppermost-portion first sidewall, a stair-step being laterally between the lower-portion first sidewall and the uppermost-portion first sidewall; the lowest-portion first sidewall being laterally-outward beyond the uppermost-portion first sidewall and the lower-portion first sidewall, the lowest-portion second sidewall being laterally-between the uppermost-portion first and second sidewalls;
covering material laterally over all of the uppermost-portion first and second sidewalls and directly above the stair-step; and
the lower portion comprising a vertically-elongated and sealed void space directly below the stair-step.

20. The structure of claim 19 wherein the covering material is directly against the conductive material of the uppermost-portion first sidewall.

21. The structure of claim 19 wherein the covering material comprises a composition different from that of the conductive material of the uppermost-portion first sidewall.

22. The structure of claim 19 wherein the covering material is insulative.

23. The structure of claim 19 wherein the covering material is not insulative.

24. The structure of claim 19 wherein the covering material has a maximum thickness no greater than 100 Angstroms.

25. The structure of claim 19 as part of a memory cell.

26. The structure of claim 19 as part of a DRAM cell.

27. The structure of claim 19 wherein the lowest portion is thicker than the lower portion.

28. The structure of claim 19 wherein the lower portion is thicker than the uppermost portion.

29. The structure of claim 19 wherein,
the lowest portion is thicker than the lower portion; and
the lower portion is thicker than the uppermost portion.

30. A plurality of elevationally-elongated conductive structures of integrated circuitry, the plurality comprising a first set of the conductive structures and a second set of the conductive structures, comprising:
the conductive structures in the first and second sets individually comprising:
conductive material electrically coupled to and extending upwardly relative to a lower node, the conductive material comprising an uppermost portion, a lower portion directly below the uppermost portion, and a lowest portion directly below the lower portion; the uppermost portion, the lower portion, and the lowest portion respectively having opposing first and second sidewalls in a same vertical cross-section;
the uppermost-portion first sidewall being laterally-between the lowest-portion first and second sidew

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Wang Kuo-Chen

Classifications

• H10P50/266

  by vapour etching only · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/043 Primary

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H01L27/10888

  Electricity · mapped topic