Transient voltage suppressor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10978441-B2
Application number	US-201715711146-A
Country	US
Kind code	B2
Filing date	Sep 21, 2017
Priority date	Sep 23, 2016
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

First claim

The invention claimed is:

1. A transient voltage suppressor, comprising:
a first semiconductor layer with a first doping type;
a first buried layer with a second doping type, which is located in said first semiconductor layer and exposed by said first semiconductor layer;
a second semiconductor layer with said second doping type, which is located on said first buried layer;
a first doped region with said first doping type, which is located in said second semiconductor layer and exposed by said second semiconductor layer;
a gate stack layer on said second semiconductor layer, which comprises a gate dielectric layer and a gate conductor layer on said gate dielectric layer;
conductive vias with said first doping type, which are adjacent to said gate stack layer and extend to said first semiconductor layer or into said first semiconductor layer;
a first electrode electrically connected with said first doped region;
a second electrode electrically connected with said gate conductor layer; and
a third electrode electrically connected with said first semiconductor layer,
wherein said second electrode and said third electrode are connected electrically, said gate stack layer is not in direct contact with said first buried layer.

2. The transient voltage suppressor according to claim 1 , wherein, when a voltage difference between said second electrode and said first electrode reaches a first voltage threshold, an inversion layer with said first doping type is formed on a surface of said second semiconductor layer under said gate stack layer and said first doped region is electrically connected with said conductive vias through said inversion layer.

3. The transient voltage suppressor according to claim 2 , wherein said first voltage threshold has an absolute value greater than a reverse breakdown voltage of a first PN junction between said first semiconductor layer and said first buried layer.

4. The transient voltage suppressor according to claim 3 , wherein said first voltage threshold has an absolute value greater than twice an applied voltage of said transient voltage suppressor.

5. The transient voltage suppressor according to claim 1 , wherein said first semiconductor layer comprises a semiconductor substrate with said first doping type and a second buried layer with said first doping type,
said first buried layer is located in a first region of said semiconductor substrate and exposed by said semiconductor substrate,
said second buried layer is located in a second region of said semiconductor substrate and exposed by said semiconductor substrate, and
said conductive vias extend to said second buried layer or into said second buried layer.

6. The transient voltage suppressor according to claim 5 , further comprising:
a third semiconductor layer with said first doping type, which is located on said second buried layer;
a second doped region with said second doping type, which is located in said third semiconductor layer and exposed by said third semiconductor layer; and
a fourth electrode electrically connected with said second doped region,
wherein said fourth electrode and said first electrode are electrically connected.

7. The transient voltage suppressor according to claim 1 , wherein said conductive vias are located at both sides of said second semiconductor layer and are reused as isolation structures of said transient voltage suppressor.

8. The transient voltage suppressor according to claim 1 , wherein said first doping type is P-type, and said second doping type is N-type.

9. A transient voltage suppressor, comprising:
a first semiconductor layer with a first doping type;
a first buried layer with a second doping type, which is located in said first semiconductor layer and exposed by said first semiconductor layer;
a second semiconductor layer with said second doping type, which is located on said first buried layer;
a first doped region with said first doping type, which is located in said second semiconductor layer and exposed by said second semiconductor layer;
a gate stack layer on said second semiconductor layer, which comprises a gate dielectric layer and a gate conductor layer on said gate dielectric layer;
conductive vias with said first doping type, which are adjacent to said gate stack layer and extend to said first semiconductor layer or into said first semiconductor layer;
a first electrode electrically connected with said first doped region;
a second electrode electrically connected with said gate conductor layer; and
a third electrode electrically connected with said first semiconductor layer,
wherein said second electrode and said third electrode are connected electrically, said first doped region has a bottom surface lower than a bottom surface of said gate stack layer which covers a top portion of said second semiconductor layer, said top region is located between said first region and one of said conductive vias.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yin Dengping
• Wang Shijun
• Yao Fei

Classifications

• H10P14/6349

  Deposition of epitaxial materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D8/20

  Breakdown diodes, e.g. avalanche diodes · CPC title

• H10D64/111

  Field plates · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title