Systems in packages including wide-band phased-array antennas and methods of assembling same

Patent metadata

Field	Value
Publication number	US-10978434-B2
Application number	US-202016774904-A
Country	US
Kind code	B2
Filing date	Jan 28, 2020
Priority date	Dec 13, 2017
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

First claim

The invention claimed is:

1. A method of assembling a wide-band phased-array antenna in a system in package, comprising:
embedding a processor die and a radio frequency integrated circuit (RFIC) die in a semiconductor device package, wherein the processor die is mated at a first surface with a redistribution layer (RDL), and wherein the RFIC die is embedded with a first surface facing opposite the processor die first surface;
forming a wide-band phased-array antenna module under conditions to include a vertical-line interconnect that is at least partially surrounded with a ground-voltage plating layer in a through-hole in a semiconductive substrate; and
assembling the wide-band phased-array antenna module to the semiconductor device package under conditions to allow at least one vertical-line interconnect to each contact a maximum of one electrical bump disposed on a bond pad of the RFIC die.

2. The method of claim 1 , wherein the processor die and RFIC die are configured side-by-side, and wherein the RFIC die is at least partially surrounded within a through-mold trench that is formed to laterally surround the RFIC die.

3. The method of claim 1 , wherein the wide-band phased-array antenna module is formed with a plurality of vertical-line interconnects that pass through the semiconductive substrate, wherein each vertical-line interconnect is at least partially surrounded with the ground-voltage plating layer, and wherein each vertical-line interconnect is insulated with a first dielectric layer that contacts the semiconductive substrate on a top surface that is opposite to a bottom surface, and wherein the first dielectric layer is also formed with the plurality of through-holes.

4. The method of claim 3 , further including:
forming the ground-voltage plating layer on the top surface of the semiconductor substrate, within the plurality of through-holes, and on the bottom surface; and
removing the ground-voltage plating layer from the top surface; followed by
forming the first dielectric layer on the top surface, within the plurality of through holes, and on the ground voltage plating layer that covers the bottom surface; and
opening the plurality of through holes under conditions to retain the first dielectric layer on the ground voltage plating in the plurality of through holes; and
forming the at least one vertical-line interconnect within one of the plurality of through holes.

5. The method of claim 1 , wherein the redistribution layer includes an electrical bump array, further including:
mating a hoard coupled to the electrical bump array disposed on the semiconductor device package on a land side.

6. The method of claim 5 , further including coupling the board to an external shell.

7. The method of claim 1 , further including coupling the processor die and the RFIC die to a chipset that includes a memory module, a memory-controller hub and a platform controller hub.

8. The method of claim 1 , further including forming a through-mold trench to form a shielding wall to separate the RFIC die from the processor die, and from a memory module.

9. A method of assembling a wide-band phased-array antenna in a system in package, comprising:
locating a processor die and a radio frequency integrated circuit (RFIC) die in a semiconductor device package, wherein the processor die includes a first surface transistor active area coupled to a redistribution layer (RDL), and wherein the RFIC die is embedded with a first surface transistor active area facing opposite the processor die first surface transistor active area; and
assembling a wide-band phased-array antenna module to the semiconductor device package under conditions to allow at least one vertical-line interconnect to each contact a maximum of one electrical bump disposed on a bond pad of the RFIC die.

10. The method of claim 9 , further including forming the wide-band phased-array antenna module under conditions to include the at least one vertical-line interconnect to be at least partially surrounded with a ground-voltage plating layer in a through-hole in a semiconductive substrate.

11. The method of claim 9 , wherein the processor die and RFIC die are configured side-by-side, and wherein the RFIC die is at least partially surrounded within a through-mold trench that is formed to laterally surround the RFIC die.

12. The method of claim 11 , further including forming the wide-band phased-array antenna module under conditions to include the at least one vertical-line interconnect to be at least partially surrounded with a ground-voltage plating layer in a through-hole in a semiconductive substrate.

13. The method of claim 12 , wherein the wide-band phased-array antenna module is formed with a plurality of vertical-line interconnects that pass through the semiconductive substrate, wherein each vertical-line interconnect is at least partially surrounded with the ground-voltage plating layer, and wherein each vertical-line interconnect is insulated with a first dielectric layer that contacts the semiconductive substrate on a top surface that is opposite to a bottom surface, and wherein the first dielectric layer is also formed with the plurality of through-holes.

14. The method of claim 13 , further including:
forming the ground-voltage plating layer on the top surface of the semiconductor substrate, within the plurality of through-holes, and on the bottom surface; and
removing the ground-voltage plating layer from the top surface; followed by
forming the first dielectric layer on the top surface, within the plurality of through holes, and on the ground voltage plating layer that covers the bottom surface; and
opening the plurality of through holes under conditions to retain the first dielectric layer on the ground voltage plating in the plurality of through holes; and
forming the at least one vertical-line interconnect within one of the plurality of through holes.

15. The method of claim 9 , wherein the redistribution layer includes an electrical bump array, further including:
mating a board coupled to the electrical bump array disposed on the semiconductor device package on a land side.

16. The method of claim 15 , further including wherein coupling the board to an external shell.

17. The method of claim 9 , further including coupling the processor die and the RFIC die to a chipset that includes a memory module, a memory-controller hub and a platform controller hub.

18. A method comprising:
forming a processor die and a radio-frequency integrated circuit (RFIC) die to be embedded in a semiconductor device package, wherein the processor die includes a first surface transistor active area disposed against a redistribution layer (RDL), wherein the RFIC die includes a first surface transistor active area facing opposite the processor die first surface;
assembling a wide-band phased-array antenna module to the semiconductor device package, wherein the RFIC die is coupled to the wide-band phased-array antenna module with at least one vertical-line interconnect, wherein the vertical-line interconnect is at least partially surrounded by a grounded voltage source, and wherein the RFIC die is isolated within a through-mold trench; and
mating a board to be coupled to an electrical bump array disposed on the semiconductor device package on a land side of the RDL.

19. The method of claim 18 , further including:
assembling the processor die and the RFIC die to a computing system that includes a chipset with at least two of a memory module, a memory controller hub, and a platform contr

Assignees

• Intel Corp

Inventors

• Cheah Bok Eng
• Kong Jackson Chung Peng
• Koh Boon Ping
• Ooi Kooi Chi

Classifications

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W44/248

  for antennas · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title