Reducing loss in stacked quantum devices

Patent metadata

Field	Value
Publication number	US-10978425-B2
Application number	US-201616333020-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Sep 13, 2016
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

The proposed device includes a first chip (102) comprising a superconducting quantum bit and a second chip (104) bonded to the first chip, the second chip including a substrate (108) having first and second opposing surfaces. The first surface (101) facing the first chip includes a layer (105) of superconductor material which includes a first circuit element. The second chip further includes a second layer (107) on the second surface (103) which includes a second circuit element, and a through connector (109) that extends from the first surface to the second surface and electrically connects a portion of the superconductor material layer to the second circuit element.

First claim

What is claimed is:

1. A device comprising:
a first chip comprising a qubit; and
a second chip bonded to the first chip, the second chip comprising a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip further comprises
a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material comprising a first circuit element,
a plurality of deposited layers on the second surface of the substrate, the plurality of deposited layers comprising a first deposited dielectric layer and a deposited superconductor layer, wherein the plurality of deposited layers form a second circuit element, and
a connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects the first circuit element to the second circuit element,

wherein there is no deposited dielectric material in direct contact with the first surface of the substrate or in direct contact with a surface of the single layer of superconductor material that faces the first chip,
wherein the first circuit element comprises a measurement readout resonator operably coupled to the qubit of the first chip, and
wherein the first deposited dielectric layer includes silicon and the second circuit element is an amplifier.

2. The device of claim 1 , wherein the device comprises a bump bond between the first chip and the single layer of superconductor material on the first surface of the substrate, wherein the bump bond is arranged to couple data between the qubit on the first chip and the first circuit element.

3. The device of claim 2 , wherein the bump bond comprises indium.

4. The device of claim 1 , wherein the single layer of superconductor material comprises a wire bond pad in addition to the first circuit element.

5. The device of claim 4 , wherein the single layer of superconductor material comprises a transmission line in addition to the first circuit element and the wire bond pad, the wire bond pad being electrically connected to the transmission line and the transmission line being arranged to electromagnetically couple or electrically couple to the first circuit element.

6. The device of claim 1 , wherein the connector extends through an opening in the substrate.

7. The device of claim 1 , wherein the plurality of deposited layers on the second surface of the substrate comprises multiple layers of wiring and dielectric film.

8. The device of claim 1 , wherein the plurality of deposited layers on the second surface of the substrate further comprises a parallel plate capacitor, a crossover wiring, an amplifier, a resonator, wiring comprising multiple layers of superconductor material, or a Josephson logic circuit.

9. The device of claim 1 , wherein the substrate comprises single crystal silicon.

10. The device of claim 1 , wherein the substrate has a thickness between approximately 100 microns and approximately 1000 microns.

11. The device of claim 1 , wherein the connector comprises tungsten or copper.

12. The device of claim 1 , wherein the connector comprises a superconductor.

13. The device of claim 2 , wherein a thickness of the bump bond between the single layer of superconductor material and the first chip is between approximately 1 micron to approximately 10 microns.

14. The device of claim 1 , wherein the single layer of superconductor material comprises aluminum or niobium.

15. The device of claim 1 , wherein the amplifier is a parametric amplifier.

16. The device of claim 1 , wherein the plurality of deposited layers forms a Josephson logic circuit.

17. The device of claim 1 , wherein the plurality of deposited layers on the second surface of the substrate comprise a deposited dielectric layer that is silicon oxide or silicon nitride.

Assignees

• Google Llc

Inventors

• White Theodore Charles

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title