Clockless decision feedback equalization (DFE) for multi-level signals

Patent metadata

Field	Value
Publication number	US-10972319-B2
Application number	US-201816128605-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	Sep 12, 2018
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.

First claim

What is claimed is:

1. A receiver comprising:
a decision feedback equalization (DFE) loop, wherein the DFE loop includes:
a summation circuit having a first input coupled to a multi-level input, a second input, and an output;
a multi-bit quantizer including a digital-to-analog converter (DAC) having an input coupled to the output of the summation circuit and having an output, and an analog-to-digital converter (ADC) having an input coupled to the output of the DAC, and having an output;
a delay circuit having an input coupled to the output of the DAC and an output providing a multi-level feedback signal; and
a DFE tap circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the summation circuit, wherein the DFE tap circuit is configured to apply signed DFE tap weights to the multi-level feedback signal;
wherein the multi-bit quantizer comprises quantizer paths, each quantizer path having a respective slicer set to a different threshold, and wherein the multi-level feedback signal is a combination of outputs from the quantizer paths.

2. The receiver of claim 1 , wherein at least some thresholds used for the slicers are set based on the peak-to-peak value of the output of the summation circuit.

3. The receiver of claim 1 , wherein the DFE tap circuit is configured to apply different signed DFE tap weights to different quantizer paths, wherein the different signed DFE tap weights are selected based on eye analysis results.

4. The receiver of claim 3 , wherein the DFE tap circuit is configured to apply a scale to a base DFE tap weight.

5. The receiver of claim 1 , wherein the multi-level input is a four-level input, the multi-level feedback signal is a four-level feedback signal, and the multi-bit quantizer is a 2-bit quantizer.

6. The receiver of claim 1 , wherein an output of the DFE loop couples to a driver for a linear repeater.

7. A decision feedback equalization (DFE) loop comprising:
a summation circuit having a first input coupled to a multi-level input signal, a second input, and an output;
quantizer paths, each having a digital-to-analog converter (DAC) with an input coupled to the output of the summation circuit and with an output, and an analog-to-digital converter (ADC) having an input coupled to the output of the DAC, and having an output coupled to the second input of the summation circuit and configured to provide a multi-level feedback signal, wherein each quantizer path includes a respective slicer set to a different threshold and a respective analog delay circuit, and wherein the multi-level feedback signal is a combination of the outputs of the quantizer paths; and
a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.

8. The DFE loop of claim 7 , wherein at least some thresholds used for the slicers are set based on the peak-to-peak value of the output of the summation circuit.

9. The DFE loop of claim 7 , wherein different DFE tap weights are applied along each quantizer path.

10. The DFE loop of claim 9 , wherein the different DFE tap weights are selected based on eye analysis results.

11. The DFE loop of claim 7 , wherein the multi-level input is a four-level input, the multi-level feedback signal is a four-level feedback signal, and wherein the plurality of quantizer paths correspond to a 2-bit quantizer.

Assignees

• Texas Instruments Inc

Inventors

• Rane Amit

Classifications

• H04L25/085

  Arrangements for reducing interference in line transmission systems, e.g. by differential transmission · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03146 Primary

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L25/4917

  using multilevel codes · CPC title