Voltage converter and method for voltage conversion

Patent metadata

Field	Value
Publication number	US-10972004-B2
Application number	US-201816478758-A
Country	US
Kind code	B2
Filing date	Jan 26, 2018
Priority date	Jan 30, 2017
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A voltage converter includes a first to a third capacitor, a supply terminal, a first and a second clock terminal and a transfer arrangement, wherein a first electrode of the first capacitor is connected to the first clock terminal and a second electrode of the first capacitor is connected to a first node of the transfer arrangement, wherein a first electrode of the second capacitor is connected to the second clock terminal and a second electrode of the second capacitor is connected to a second node of the transfer arrangement, and wherein a first electrode of the third capacitor is permanently and directly connected to the second electrode of the first capacitor and a second electrode of the third capacitor is connected to a third node of the transfer arrangement.

First claim

We claim:

1. A voltage converter, comprising
a first, a second and a third capacitor,
a supply terminal,
a first and a second clock terminal and
a transfer arrangement,
wherein an input of the transfer arrangement is coupled to the supply terminal and an output of the transfer arrangement is coupled to an output terminal of the voltage converter,
a first electrode of the first capacitor is connected to the first clock terminal and a second electrode of the first capacitor is connected to a first node of the transfer arrangement,
a first electrode of the second capacitor is connected to the second clock terminal and a second electrode of the second capacitor is connected to a second node of the transfer arrangement,
a first electrode of the third capacitor is permanently and directly connected to the second electrode of the first capacitor and a second electrode of the third capacitor is connected to a third node of the transfer arrangement,
wherein the first and the second capacitor both have a first capacitance value and the third capacitor has a second capacitance value, and
wherein the first capacitance value is larger than the second capacitance value.

2. The voltage converter according to claim 1 , comprising
a fourth capacitor having a first electrode permanently and directly connected to the second electrode of the second capacitor and a second electrode connected to a fourth node of the transfer arrangement.

3. The voltage converter according to claim 2 , comprising
at least a Nth capacitor having a first electrode permanently and directly connected to the second electrode of the (N−2)th capacitor and a second electrode connected to a Nth node of the transfer arrangement, wherein N is an integer larger than 4.

4. The voltage converter according to claim 1 ,
wherein the transfer arrangement comprises a first, a second and a third circuit element, and
wherein the first circuit element couples the supply terminal to the first node, the second circuit element couples the first node to the second node and the third circuit element couples the second node to the third node.

5. The voltage converter according to claim 4 ,
wherein each of the first, the second and the third circuit element is realized as a diode.

6. The voltage converter according to claim 4 ,
wherein each of the first, the second and the third circuit element is realized as a field-effect transistor.

7. The voltage converter according to claim 1 ,
wherein the transfer arrangement comprises a first switching arrangement having a first and a second switch,
wherein the first switch couples the input of the transfer arrangement to the first node and the second switch couples the first node to a first intermediate node of the transfer arrangement.

8. The voltage converter according to claim 7 ,
wherein the first switching arrangement comprises a third and a fourth switch, and
wherein the third switch couples the second node to the first intermediate node of the transfer arrangement and the fourth switch couples the input of the transfer arrangement to the second node.

9. The voltage converter according to claim 7 ,
further comprising a first back-up capacitor coupling the first intermediate node to a reference potential terminal.

10. The voltage converter according to claim 7 ,
wherein the transfer arrangement comprises a second switching arrangement having a fifth and a sixth switch,
wherein the fifth switch couples the first intermediate node to the third node and the sixth switch couples the third node to a second intermediate node of the transfer arrangement.

11. The voltage converter according to claim 10 ,
further comprising a second back-up capacitor coupling the second intermediate node to the first intermediate node.

12. The voltage converter according to claim 1 ,
wherein a first clock signal is applied to the first clock terminal and a second clock signal is applied to the second clock terminal,
wherein a non-overlap time is between a pulse of the first clock signal and the following pulse of the second clock signal, and
wherein a further non-overlap time is between a pulse of the second clock signal and the following pulse of the first clock signal.

13. A method for voltage conversion, comprising
providing an input voltage to an input of a transfer arrangement,
providing a first clock signal to a first electrode of a first capacitor,
providing a second clock signal to a first electrode of a second capacitor, and
tapping an output voltage at an output of the transfer arrangement,
wherein a second electrode of the first capacitor is connected to a first node of the transfer arrangement,
a second electrode of the second capacitor is connected to a second node of the transfer arrangement, and
a first electrode of a third capacitor is permanently and directly connected to the second electrode of the first capacitor and a second electrode of the third capacitor is connected to a third node of the transfer arrangement,
wherein the transfer arrangement comprises a first switching arrangement having a first and a second switch,
wherein the first switch couples the input of the transfer arrangement to the first node and the second switch couples the first node to a first intermediate node of the transfer arrangement, and
wherein a first back-up capacitor couples the first intermediate node to a reference potential terminal.

14. A method according to claim 13 ,
wherein pulses of the first clock signal and pulses of the second clock signal alternate.

15. A voltage converter comprising:
a first capacitor, a second capacitor and a third capacitor;
a supply terminal;
a first clock terminal and a second clock terminal; and
a transfer arrangement,
wherein the voltage converter is configured such that:
an input of the transfer arrangement is coupled to the supply terminal, and an output of the transfer arrangement is coupled to an output terminal of the voltage converter,
a first electrode of the first capacitor is connected to the first clock terminal, and a second electrode of the first capacitor is connected to a first node of the transfer arrangement,
a first electrode of the second capacitor is connected to the second clock terminal, and a second electrode of the second capacitor is connected to a second node of the transfer arrangement,
a first electrode of the third capacitor is permanently and directly connected to the second electrode of the first capacitor, and a second electrode of the third capacitor is connected to a third node of the transfer arrangement,
a first clock signal is applied to the first clock terminal and a second clock signal is applied to the second clock terminal,
a non-overlap time is between a pulse of the first clock signal and the following pulse of the second clock signal, and a further non-overlap time is between a pulse of the second clock signal and the following pulse of the first clock signal,
wherein the first and the second capacitor both have a first capacitance value and the third capacitor has a second capacitance value, and
wherein the first capacitance value is larger than the second capacitance value.

Assignees

• Ams Ag

Inventors

• Lenhard Herbert
• Lueger Manfred

Classifications

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M2003/075

  Electricity · mapped topic