Selective device, memory cell, and storage unit

Patent metadata

Field	Value
Publication number	US-10971685-B2
Application number	US-201615545923-A
Country	US
Kind code	B2
Filing date	Jan 8, 2016
Priority date	Feb 10, 2015
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series.

First claim

The invention claimed is:

1. A selective device, comprising:
a first electrode;
a second electrode that faces the first electrode;
a switch device that includes a switch layer, wherein
the switch layer is between the first electrode and the second electrode, and
the switch layer is in direct contact with the first electrode; and

a non-linear resistive device that comprises a non-linear resistive layer, wherein
the non-linear resistive layer comprises at least one of boron (B), silicon (Si), or carbon (C),
the non-linear resistive layer and the switch layer are directly stacked between the first electrode and the second electrode,
the non-linear resistive device further comprises a junction field-effect transistor,
a gate electrode of the junction field-effect transistor is independently of the second electrode, and
the second electrode corresponds to a drain electrode and a source electrode of the junction field-effect transistor.

2. The selective device according to claim 1 , wherein the non-linear resistive layer further comprises one of an alloy of the at least one of boron (B), silicon (Si), or carbon (C), or a compound of the at least one of boron (B), silicon (Si), or carbon (C).

3. The selective device according to claim 1 , wherein the non-linear resistive layer further comprises one of oxide, nitride, or oxynitride of one of boron (B) or silicon (Si).

4. The selective device according to claim 1 , wherein
the non-linear resistive device is configured to:
withstand a dielectric withstanding voltage of at least 1 MV/cm, and
output a current with a current density of at least 10 MA/cm 2 at a voltage of at least 2 V.

5. The selective device according to claim 1 , wherein the switch layer is configured to:
change from a high-resistance state to a low-resistance state based on an increase of an applied voltage to a threshold voltage or higher; and
change from the low-resistance state to the high-resistance state based on a decrease of the applied voltage to the threshold voltage or lower.

6. The selective device according to claim 5 , wherein the switch layer comprises at least one of tellurium (Te), boron (B), silicon (Si), carbon (C), or nitrogen (N).

7. A memory cell, comprising:
a memory device; and
a selective device coupled to the memory device, wherein the selective device comprises:
a first electrode;
a second electrode that faces the first electrode;
a switch device that includes a switch layer, wherein
the switch layer is between the first electrode and the second electrode, and
the switch layer is in direct contact with the first electrode; and

a non-linear resistive device that comprises a non-linear resistive layer, wherein
the non-linear resistive layer comprises at least one of boron (B), silicon (Si), or carbon (C),
the non-linear resistive layer and the switch layer are directly stacked between the first electrode and the second electrode,
the non-linear resistive device further comprises a junction field-effect transistor,
a gate electrode of the junction field-effect transistor is independently of the second electrode, and
the second electrode corresponds to a drain electrode and a source electrode of the junction field-effect transistor.

8. The memory cell according to claim 7 , wherein the memory device comprises a storage layer between the first electrode and the second electrode.

9. The memory cell according to claim 8 , wherein
the storage layer comprises an ion source layer and a resistance-change layer,
the ion source layer comprises at least one of tellurium (Te), aluminum (Al), copper (Cu), zirconium (Zr), nitrogen (N), or oxygen (O), and
the resistance-change layer comprises an oxide material.

10. The memory cell according to claim 8 , further comprising
a third electrode, wherein
the storage layer and the selective device are between the first electrode and the second electrode, and
the third electrode is in between the storage layer and the selective device.

11. The memory cell according to claim 8 , wherein
the storage layer comprises at least one of a resistance-change layer, a phase-change memory layer, or a magnetic resistance-change memory layer, and
the resistance-change layer comprises a transition metal oxide.

12. A storage unit, comprising:
a plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises:
a memory device; and
a selective device coupled to the memory device, wherein the selective device comprises:
a first electrode;
a second electrode that faces the first electrode;
a switch device that includes a switch layer, wherein
the switch layer is between the first electrode and the second electrode, and
the switch layer is in direct contact with the first electrode; and

a non-linear resistive device that comprises a non-linear resistive layer, wherein
the non-linear resistive layer comprises at least one of boron (B), silicon (Si), or carbon (C),
the non-linear resistive layer and the switch layer are directly stacked between the first electrode and the second electrode,
the non-linear resistive device further comprises a junction field-effect transistor,
a gate electrode of the junction field-effect transistor is independently of the second electrode, and
the second electrode corresponds to a drain electrode and a source electrode of the junction field-effect transistor.

13. The storage unit according to claim 12 , further comprising a plurality of row lines and a plurality of column lines, wherein the plurality of memory cells is adjacent to each of a plurality of intersecting regions of the plurality of row lines and the plurality of column lines.

14. A selective device, comprising:
a first electrode;
a second electrode that faces the first electrode;
a switch device that includes a switch layer, wherein
the switch layer is between the first electrode and the second electrode, and
the switch layer is in direct contact with the first electrode; and

a non-linear resistive device that comprises a constant-current diode, wherein
the non-linear resistive device and the switch device are directly stacked between the first electrode and the second electrode,
the constant-current diode is a junction field-effect transistor,
a gate electrode of the junction field-effect transistor is independently of the second electrode, and
the second electrode corresponds to a drain electrode and a source electrode of the junction field-effect transistor.

15. The selective device according to claim 14 , wherein the non-linear resistive device further comprises at least one of boron (B), silicon (Si), or carbon (C).

16. The selective device according to claim 14 , wherein
the non-linear resistive device is configured to:
withstand a dielectric withstanding voltage of at least 1 MV/cm, and
output a current with a current density of at least 10 MA/cm 2 at a voltage of at least 2 V.

Assignees

• Sony Corp

Inventors

• Ohba Kazuhiro
• Ikarashi Minoru

Classifications

• H01L27/1052

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L49/02

  Electricity · mapped topic

• H01L45/1253 Primary

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic