Epitaxial structures of a semiconductor device having a wide gate pitch

Patent metadata

Field	Value
Publication number	US-10971625-B2
Application number	US-201916458178-A
Country	US
Kind code	B2
Filing date	Jun 30, 2019
Priority date	Jun 30, 2019
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

First claim

What is claimed is:

1. A semiconductor device comprising:
an array of active regions, gate stacks and substantially uniform epitaxial structures, the gate stacks including a first gate stack and a second gate stack over an active region, the second gate stack being adjacent to the first gate stack;
an active pillar between the first gate stack and the second gate stack, wherein the active pillar comprises a doped conductive region;
two substantially uniform epitaxial structures between the first and second gate stacks and are separated by the active pillar, wherein each of the substantially uniform epitaxial structures has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device; and
a contact structure over the active pillar that is positioned equidistant from the first gate stack and the second gate stack.

2. The semiconductor device of claim 1 , wherein the active pillar has a top surface substantially coplanar with a top surface of the active region.

3. The semiconductor device of claim 1 , further comprises a dielectric segment over the active pillar.

4. The semiconductor device of claim 1 , wherein the doped conductive region is at an upper portion of the active pillar.

5. The semiconductor device of claim 1 , wherein the contact structure has a width at least as wide as the active pillar and electrically connects the two substantially uniform epitaxial structures.

6. The semiconductor device of claim 1 , wherein each of the substantially uniform epitaxial structures has a top surface substantially coplanar with a top surface of the active pillar.

7. A method of forming a semiconductor device comprising:
providing an active region over a substrate, the active region having a top surface;
forming a first gate stack and a second gate stack over the active region, the second gate stack being adjacent to the first gate stack;
forming an active pillar in the active region between the first gate stack and the second gate stack, wherein the active pillar has a top surface substantially coplanar with the top surface of the active region;
forming a doped conductive region in the active pillar;
forming substantially uniform epitaxial structures between the first and second gate stacks that are positioned adjacent to the active pillar in the active region, wherein each of the substantially uniform epitaxial structures has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device; and
forming a contact structure over the active pillar.

8. The method of claim 7 , wherein forming the active pillar further comprises:
depositing a dielectric layer over the active region, the first gate stack and the second gate stack;
forming openings in the dielectric layer to expose portions of the active region; and
removing the exposed portions of the active region to form the active pillar in the active region.

9. The method of claim 8 , wherein removing the exposed portions of the active region further comprises using the first gate stack, the second gate stack and a pillar mask portion of the patterning layer interposed therebetween as masking features to form the active pillar.

10. The method of claim 9 , wherein removing the exposed portions of the active region further comprises forming a first cavity between the first gate stack and the pillar mask and a second cavity between the pillar mask and the second gate stack; and
the substantially uniform epitaxial structures are formed in the first and second cavities adjacent to the active pillar and are formed with top surfaces that are substantially coplanar with the top surface of the active region.

11. The method of claim 10 , wherein the first and second cavities are formed by a dry etching process.

12. The method of claim 7 , wherein the active pillar has a pre-determined width that defines widths of the epitaxial structures to be substantially equal to a minimum gate-to-gate spacing of the semiconductor device.

13. The method of claim 7 , wherein forming the doped conductive region comprises implanting the active pillar with dopants to electrically connect the substantially uniform epitaxial structures adjacent to the active pillar in the active region.

14. The method of claim 7 , wherein forming the contact structure over the active pillar further comprises:
depositing an insulating layer over and between the first and second gate stacks;
forming a contact opening having a width at least as wide as the active pillar in the insulating layer; and
filling the contact opening with a conductive material to form the contact structure.

15. A semiconductor device comprising:
an active region;
a first gate stack and a second gate stack over the active region, the second gate stack being adjacent to the first gate stack;
an active pillar in the active region between the first gate stack and the second gate stack, wherein the active pillar comprises a doped conductive region;
two substantially uniform epitaxial structures separated by the active pillar between the first and second gate stacks, wherein each of the substantially uniform epitaxial structures has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device; and
a contact structure over the active pillar.

16. The semiconductor device of claim 15 , wherein the contact structure is equidistant from the first gate stack and the second gate stack.

17. The semiconductor device of claim 15 , wherein the contact structure electrically contacts the two substantially uniform epitaxial structures.

18. The semiconductor device of claim 15 , wherein the contact structure has a width at least as wide as the active pillar.

Assignees

• Globalfoundries Us Inc

Inventors

• Aquilino Michael V
• Jaeger Daniel
• Gu Man
• Morgenfeld Bradley
• Wang Haiting
• Duggimpudi Kavya Sree
• Zheng Wang

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/025

  forming recessed gates, e.g. by using local oxidation · CPC title

• H10D62/149

  Source or drain regions of field-effect devices · CPC title