Driver circuit and its working method and display device

US10971070B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10971070-B2
Application numberUS-201916673071-A
CountryUS
Kind codeB2
Filing dateNov 4, 2019
Priority dateJan 4, 2019
Publication dateApr 6, 2021
Grant dateApr 6, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a driver circuit and its working method and a display device. The driver circuit includes: a driver chip coupled with a plurality of signal lines; a plurality of signal line leads that are corresponding to the plurality of signal lines in a one-to-one manner; and a plurality of short-circuit shielding circuits that are corresponding to the plurality of signal line leads in a one-to-one manner. Each of the plurality of short-circuit shielding circuits is coupled between corresponding one of the plurality of signal line leads and corresponding one of the plurality of signal lines, and is configured to turn on or off a connection between the corresponding one of the plurality of signal line leads and the corresponding one of the plurality of signal lines.

First claim

Opening claim text (preview).

What is claimed is: 1. A driver circuit applicable to a display substrate, comprising: a driver chip coupled with a plurality of signal lines; a plurality of signal line leads corresponding to the plurality of signal lines in a one-to-one manner; and a plurality of short-circuit shielding circuits corresponding to the plurality of signal line leads in a one-to-one manner; wherein each of the plurality of short-circuit shielding circuits is coupled between corresponding one of the plurality of signal line leads and corresponding one of the plurality of signal lines, and is configured to turn on or off a connection between the corresponding one of the plurality of signal line leads and the corresponding one of the plurality of signal lines, wherein the plurality of signal lines include first signal lines configured to transmit a positive voltage signal and second signal lines configured to transmit a negative voltage signal; each of the plurality of short-circuit shielding circuits includes one of a first diode and a second diode; an anode of the first diode is coupled with one signal line lead which is one of the plurality of signal line leads and which is coupled with the short-circuit shielding circuit including the first diode; and a cathode of the first diode is coupled with corresponding one of the first signal lines; a cathode of the second diode is coupled with one signal line lead which is one of the plurality of signal line leads and which is coupled with the short-circuit shielding circuit including the second diode; and an anode of the second diode is coupled with corresponding one of the second signal lines. 2. The driver circuit of claim 1 , wherein each of the plurality of short-circuit shielding circuit is further coupled with a gate control terminal; each of the plurality of short-circuit shielding circuit is configured to, under control of the gate control terminal, turn on or off a connection between one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuit and one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuit. 3. The driver circuit of claim 2 , wherein the gate control terminal includes a first control terminal and a second control terminal; each of the plurality of short-circuit shielding circuit includes a first control sub-circuit and a second control sub-circuit; the first control sub-circuit is coupled with the first control terminal, a first node and the one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuit, respectively; the first control sub-circuit is configured to, under control of the first control terminal, turn on or off a connection between the first node and the one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuit; and the second control sub-circuit is coupled with the second control terminal, the first node and the one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuit, respectively; the second control sub-circuit is configured to, under control of the second control terminal, turn on or off a connection between the first node and the one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuit. 4. The driver circuit of claim 3 , wherein the first control sub-circuit includes a first switching transistor; a gate of the first switching transistor is coupled with the first control terminal; a first electrode of the first switching transistor is coupled with the one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuit; and a second electrode of the first switching transistor is coupled with the first node; the second control sub-circuit includes a second switching transistor; a gate of the second switching transistor is coupled with the second control terminal; a first electrode of the second switching transistor is coupled with the first node; a second electrode of the second switching transistor is coupled with the one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuit. 5. The driver circuit of claim 4 , wherein the first control terminal is coupled with the second control terminal. 6. The driver circuit of claim 3 , wherein the first control terminal is coupled with the second control terminal. 7. The driver circuit of claim 1 , wherein the plurality of signal lines include one or more of a data line, a power line, and a gate drive signal line; the gate drive signal line is applied in a gate drive circuit of the display substrate; and the plurality of signal line leads include one or more of a data-line lead coupled with the data line, a power-line lead coupled with the power line and a gate-drive-signal-line lead coupled with the gate drive signal line. 8. A display device comprising the driver circuit of claim 1 . 9. A driver-circuit working method, which is applied to the driver circuit of claim 1 , the working method comprising: in a lighting test period during which a display substrate is subjected to a lighting test, turning on, by each of the plurality of short-circuit shielding circuits, a connection between one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuits and one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuits; in a module lighting period during which the driver chip drives the display substrate to realize display function, turning off, by each of the plurality of short-circuit shielding circuits, the connection between the one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuits and the one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuits; and providing, by the driver chip, corresponding driving signals for the plurality of signal lines. 10. The working method of claim 9 , wherein the plurality of signal lines include first signal lines configured to transmit a positive voltage signal and second signal lines configured to transmit a negative voltage signal, and each of the plurality of short-circuit shielding circuits includes one of a first diode and a second diode; an anode of the first diode is coupled with one of the plurality of signal line leads that is coupled with the short-circuit shielding circuit including the first diode; and a cathode of the first diode is coupled with corresponding one of the first signal lines; a cathode of the second diode is coupled with one of the plurality of signal line leads that is coupled with the short-circuit shielding circuit including the second diode; and an anode of the second diode is coupled with corresponding one of the second signal lines; in the lighting test period, turning on, by each of the plurality of short-circuit shielding circuits, a connection between one of the plurality of signal line leads that is coupled with the each of the plurality of short-circuit shielding circuits and one of the plurality of signal lines that is coupled with the each of the plurality of short-circuit shielding circuits, includes: in the lighting test period, turning on, by the first diode, a connection between the one of the plurality of signal line leads that is coupled with the short-circuit shielding circuit including the first diode a

Assignees

Inventors

Classifications

  • Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • G09G3/3208Primary

    organic, e.g. using organic light-emitting diodes [OLED] · CPC title

  • G09G3/3258Primary

    with pixel circuitry controlling the voltage across the light-emitting element · CPC title

  • G09G3/3225Primary

    using an active matrix · CPC title

  • Calibration of display systems · CPC title

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Frequently asked questions

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What does patent US10971070B2 cover?
The present disclosure provides a driver circuit and its working method and a display device. The driver circuit includes: a driver chip coupled with a plurality of signal lines; a plurality of signal line leads that are corresponding to the plurality of signal lines in a one-to-one manner; and a plurality of short-circuit shielding circuits that are corresponding to the plurality of signal lin…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3208. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).