Digital-to-analog converter and electronic system including the same

Patent metadata

Field	Value
Publication number	US-10965299-B1
Application number	US-202016887535-A
Country	US
Kind code	B1
Filing date	May 29, 2020
Priority date	Nov 11, 2019
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A digital-to-analog converter (DAC) includes a current array having a plurality of unit cells in a plurality of rows and a plurality of columns, an arbitrary switch box and processing circuitry configured to randomly select a subset of rows among the plurality of rows based on a plurality of first row selection signals, the subset of rows including first unit cells among the plurality of unit cells, randomly select one row among the plurality of rows based on a plurality of second row selection signals, select a subset of columns among the plurality of columns based on column selection signals, second unit cells among the plurality of unit cells being included in both the one row and the subset of columns, and generate an analog output signal corresponding to a digital input signal based on the first unit cells and the second unit cells.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) comprising:
a current array including a plurality of unit cells, the plurality of unit cells being arranged in a matrix formation including a plurality of rows and a plurality of columns;
an arbitrary switch box configured to change an arrangement order of bits based on a random number; and
processing circuitry configured to
generate (2 M +1) first bits based on an upper M bits of a digital input signal of N bits, N being an integer greater than or equal to two and M being an integer less than N,
generate a plurality of first row selection signals and a plurality of second row selection signals based on a plurality of randomized first bits, the plurality of randomized first bits being obtained from the arbitrary switch box based on the (2 M +1) first bits,
generate 2 (N−M) column selection signals based on a lower (N−M) bits of the digital input signal,
randomly select a subset of rows among the plurality of rows based on the plurality of first row selection signals, the subset of rows including first unit cells among the plurality of unit cells,
randomly select one row among the plurality of rows based on the plurality of second row selection signals,
select a subset of columns among the plurality of columns based on the 2 (N−M) column selection signals, second unit cells among the plurality of unit cells being included in both the one row and the subset of columns, and
generate an analog output signal corresponding to the digital input signal based on the first unit cells and the second unit cells.

2. The digital-to-analog converter of claim 1 , wherein
the subset of rows are consecutive rows; and
the one row a row subsequent to a last row among the subset of rows.

3. The digital-to-analog converter of claim 2 , wherein
the arbitrary switch box is configured to generate the plurality of randomized first bits by randomly changing the arrangement order of the (2 M +1) first bits; and
the processing circuitry is configured to
randomly select the subset of rows based on a randomization provided by the plurality of randomized first bits, and
randomly select the one row based on the randomization without performing additional randomization.

4. The digital-to-analog converter of claim 2 , wherein the subset of columns selected are consecutive columns.

5. The digital-to-analog converter of claim 4 , wherein the subset of columns are a first column through a Y-th column among the plurality of columns included in the one row, Y being a positive integer.

6. The digital-to-analog converter of claim 1 , wherein the processing circuitry is configured to generate the analog output signal based on a current signal generated by the first unit cells and the second unit cells.

7. The digital-to-analog converter of claim 1 , wherein
2 M bits among the (2 M +1) first bits correspond to a value of the upper M bits of the digital input signal; and
one bit not included in the 2 M bits among the (2 M +1) first bits is a pointer bit for a dynamic element matching (DEM).

8. The digital-to-analog converter of claim 7 , wherein a quantity of bits having a first bit value among the 2 M bits is equal to the value of the upper M bits of the digital input signal.

9. The digital-to-analog converter of claim 7 , wherein the pointer bit always has a first bit value.

10. The digital-to-analog converter of claim 7 , wherein the one row is selected based on the pointer bit.

11. The digital-to-analog converter of claim 1 , wherein processing circuitry is configured to generate 2 (N−M) second bits corresponding to a value of the lower (N−M) bits of the digital input signal, the 2 (N−M) column selection signals corresponding to the 2 (N−M) second bits.

12. The digital-to-analog converter of claim 11 , wherein a quantity of bits having a first bit value among the 2 (N−M) second bits is equal to the value of the lower (N−M) bits of the digital input signal.

13. The digital-to-analog converter of claim 1 , wherein the arbitrary switch box is configured to change an arrangement order of bits based on a quantity of random numbers equal to M.

14. The digital-to-analog converter of claim 13 , wherein the arbitrary switch box includes at least one stage and a plurality of switches.

15. The digital-to-analog converter of claim 14 , wherein a number of the at least one stage included in the arbitrary switch box is equal to M.

16. The digital-to-analog converter of claim 1 , wherein each of the plurality of unit cells includes a current source.

17. A digital-to-analog converter (DAC) comprising:
a current array including a plurality of unit cells, the plurality of unit cells being arranged in a matrix formation including a plurality of rows and a plurality of columns;
an arbitrary switch box configured to change an arrangement order of bits based on a random number; and
processing circuitry configured to
generate (2 M +1) first bits based on an upper M bits of a digital input signal of N bits, N being an integer greater than or equal to two and M being an integer less than N,
generate a plurality of first column selection signals and a plurality of second column selection signals based on a plurality of randomized first bits, the plurality of randomized first bits being obtained from the arbitrary switch box based on the (2 M +1) first bits,
generate 2 (N−M) row selection signals based on a lower (N−M) bits of the digital input signal,
randomly select a subset of columns among the plurality of columns based on the plurality of first column selection signals, the subset of columns including first unit cells among the plurality of unit cells,
randomly select one column among the plurality of columns based on the plurality of second column selection signals,
select a subset of rows among the plurality of rows based on the 2 (N−M) row selection signals, second unit cells among the plurality of unit cells being included in both the one column and the subset of rows, and
generate an analog output signal corresponding to the digital input signal based on the first unit cells and the second unit cells.

18. The digital-to-analog converter of claim 17 , wherein
the subset of columns are consecutive columns,
the one column is a column subsequent to a last column among the subset of columns;
the arbitrary switch box is configured to generate the plurality of randomized first bits by randomly changing the arrangement order of the (2 M +1) first bits; and
the processing circuitry is configured to
randomly select the subset of columns based on a randomization provided by the plurality of randomized first bits, and
randomly select the one column based on the randomization without performing additional randomization.

19. An electronic system comprising:
a first digital-to-analog converter (DAC) configured to generate a first analog output signal based on a first digital input signal, wherein the first digital-to-analog converter includes
a current array including a plurality of unit cells, the plurality of unit cells being in a matrix formation including a plurality of rows and a plurality of columns,
an arbitrary switch box configured to change an arrangement order of bits based on a random number, and
processing circuitry configured to
generate (2 M +1) first bits based on an upper M bits among the first digital input signal of N bits, N being an integer greater than or equal to two and M being an integer less than N,
generate a plurality of first row selection signals and a p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jungho
• Choi Michael
• Koo Byungwoo
• Roh Hyungdong
• Do Sunghan
• Cho Youngjae

Classifications

• H03M7/165

  Conversion to or from thermometric code · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/066

  by continuously permuting the elements used, i.e. dynamic element matching · CPC title

• H03M1/685

  the quantisation value generators of both converters being arranged in a common two-dimensional array · CPC title

• H03M1/0673 Primary

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title