DAC current source matrix patterns with gradient error cancellation

Patent metadata

Field	Value
Publication number	US-9094042-B2
Application number	US-201313963788-A
Country	US
Kind code	B2
Filing date	Aug 9, 2013
Priority date	Aug 9, 2013
Publication date	Jul 28, 2015
Grant date	Jul 28, 2015

Abstract

First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) comprising:
an array of current elements configured to supply current using thermometer decoding of a code corresponding to at least a portion of a digital signal to be converted;
wherein for a majority of current elements in the array, pairs of consecutive current elements of the array are placed substantially symmetrically around a center of the array, such that for each of the pairs, a first and second current element are offset from the center of the array in a substantially equal and opposite direction.

2. The DAC as recited in claim 1 wherein the center of the array is a two dimensional center of the array.

3. The DAC as recited in claim 1 wherein spatial separation for current elements of the pairs corresponding to codes for larger signal amplitudes is larger compared to spatial separation for the current elements of pairs corresponding to codes for smaller signal amplitudes.

4. The DAC as recited in claim 3 wherein the smaller signal amplitudes are for mid-scale codes.

5. The DAC as recited in claim 3 wherein the DAC is a differential or single-ended current steering DAC.

6. The DAC as recited in claim 3 wherein the spurious free dynamic range is substantially constant across input signal amplitudes.

7. The DAC as recited in claim 1 wherein the current elements are metal oxide semiconductor (MOS) transistors or bipolar junction transistors.

8. The DAC as recited in claim 1 wherein the current elements are not split into sub-elements.

9. The DAC as recited in claim 1 wherein current elements of the pairs corresponding to codes for larger signal amplitudes are farther from the center of the array as compared to current elements of the pairs corresponding to codes for smaller signal amplitudes.

10. The DAC as recited in claim 1 wherein for each of the pairs of consecutive current elements, a first current element of the pair is turned off in response to a minimum decrement of a current value of the control code and a second current element is turned on in response to a minimum increment of the current value of the control code.

11. A method of operating a digital to analog converter providing thermometer decoding using an array of current elements, comprising:
in response to a digital control code, turning on a first current element offset from a center of the array and supplying a first current corresponding to the digital control code generated in part using the first current element;
responsive to a minimum increment to the digital control code, turning on a second current element, offset from the center of the array in a substantially equal and opposite direction as the first current element, as part of generating a second current corresponding to the digital control code with the minimum increment.

12. A digital-to-analog converter (DAC) comprising:
an array of current elements configured to provide thermometer decoding of an input code, wherein for a majority of current elements in the array, pairs of consecutive current elements of the array are arranged with a first current element of each pair being placed with respect to a zero error contour of a second order gradient to have a positive error and a second current element of the pair is placed to have a negative error of approximately a same magnitude as the positive error.

13. The digital-to-analog converter as recited in claim 12 wherein for a majority of current elements in the array, pairs of consecutive current elements of the array are arranged with one current element of each pair being placed closer to a center of the array and the other current element of each pair being placed closer to an outer portion of the array to thereby provide the positive error and the negative error.

14. The digital-to-analog converter as recited in claim 12 wherein the current elements of the array comprise:
at least a first and a second sub-element, the first and second sub-element of each of the current elements being placed substantially symmetrically around the center of the array, such that the first sub-element and second sub-elements are offset in a substantially equal and opposite direction from the center of the array.

15. The digital-to-analog converter as recited in claim 12 wherein a majority of mid-scale codes are placed at or near the zero error contour.

16. The digital-to-analog converter as recited in claim 12 wherein the digital-to-analog converter is a single-ended or differential current steering DAC.

17. The digital-to-analog converter as recited in claim 12 wherein the spurious free dynamic range is substantially constant across input signal amplitudes.

18. The DAC as recited in claim 12 wherein the current elements are one of metal oxide semiconductor (MOS) transistors or bipolar junction transistors.

19. A method of operating a digital-to-analog converter (DAC) with a plurality of pairs of current elements:
turning on a first current element of each of the pairs responsive to respective input codes indicating an amount of current to supply from a thermometer decoding section of the DAC; and
turning on a second current element of each of the pairs responsive to a thermometer code step responsive to an increment of the respective input codes, wherein one of the first and second current elements is located inside of a zero error contour of a second order gradient and another of the first and second current elements is located outside the zero error contour such that turning on the second current element offsets second order gradient effects associated with turning on the first current element.

20. The method as recited in claim 19 further comprising:
turning on the current elements by turning on at least two respective sub-elements forming each current element, the sub-elements disposed substantially symmetrically around a center location in an array of the current elements, and thereby substantially cancelling first order gradient errors associated with the current elements.

21. The method as recited in claim 19 wherein one of the pair of each of the current element pairs is located closer to a center of an array of the current elements and the second of the pair of each of the current element pairs located closer to an edge of the array.

Assignees

• Silicon Lab Inc

Inventors

• Onódy Péter
• Coban Abdulkerim L

Classifications

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0648 Primary

  by arranging the quantisation value generators in a non-sequential pattern layout, e.g. symmetrical · CPC title

• H03M1/745

  with weighted currents · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title