Low noise charge pump method and apparatus

Patent metadata

Field	Value
Publication number	US-10965276-B2
Application number	US-202016793969-A
Country	US
Kind code	B2
Filing date	Feb 18, 2020
Priority date	Sep 8, 2003
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

First claim

What is claimed is:

1. A charge pump clock generating circuit configured to generate a clock signal for a capacitive charge pump comprising at least one transfer capacitor having an input terminal and an output terminal, and a plurality of transfer capacitor coupling switches, each coupled to the clock signal and to one of the input terminal or output terminal of a corresponding one of the at least one transfer capacitor, each transfer capacitor coupling switch being switchable between a conducting state and a non-conducting state under control of the coupled clock signal, the charge pump clock generating circuit including:
(a) a ring oscillator comprising an odd number of inverting driver sections configured to output the clock signal; and
(b) active limiting circuitry associated with each driver section, the active limiting circuitry including a source current limit circuit coupled between a first voltage source and the associated driver section and configured to limit the current source capability of the associated driver section, and a sink current limit circuit coupled between the associated driver section and a common reference voltage and configured to limit the current sink capability of the associated driver section, wherein the active limiting circuitry limits output transitions dv/dt of the clock signal and reduces switching speeds of substantially all of the driver sections;
wherein the plurality of transfer capacitor coupling switches are controlled by the coupled clock signal so as to couple the input terminal of the corresponding transfer capacitor to a second voltage source during periodic first times, and to couple the output terminal of the corresponding transfer capacitor to a voltage output terminal during periodic second times that are not concurrent with the periodic first times, and
wherein the charge pump clock generating circuit is configured such that the limited output transitions dv/dt of the clock signal create periods of time that cause all transfer capacitor coupling switches coupled to a corresponding transfer capacitor to be in the non-conducting state.

2. The invention of claim 1 , wherein at least a first of the plurality of transfer capacitor coupling switches has a first gate threshold voltage and at least a second of the plurality of transfer capacitor coupling switches has a second gate threshold voltage different from the first gate threshold voltage, and wherein the clock signal during the periods of time has a voltage between the first gate threshold voltage and the second gate threshold voltage such that the at least first of the plurality of transfer capacitor coupling switches and the at least second of the plurality of transfer capacitor coupling switches are in the non-conducting state.

3. The invention of claim 1 , wherein the active current limiting circuitry for each driver section includes a capacitance coupled between the output of the driver section and the common reference.

4. The invention of claim 1 , wherein the charge pump clock generating circuit further includes a discrete capacitive element coupled to the output of the last driver section and configured to limit output transitions dv/dt of the clock signal.

5. The invention of claim 1 , wherein the clock signal is a single-phase clock signal.

6. The invention of claim 1 , wherein the ring oscillator comprises three inverting driver sections.

7. The invention of claim 1 , wherein the source current limit circuit and sink current limit circuit are configured to limit the current source capability and the current sink capability to a substantially identical magnitude.

8. The invention of claim 1 , wherein undesirable harmonic generation is reduced by a configuration of the source current limit circuit and of the sink current limit circuit that limits the current source capability and the current sink capability to a substantially identical magnitude.

9. The invention of claim 1 , wherein the charge pump clock generating circuit is embodied within a monolithic integrated circuit.

Assignees

• Psemi Corp

Inventors

• Burgener Mark L
• Kelly Dylan J
• Cable James S

Classifications

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03K3/013 Primary

  Modifications of generator to prevent operation by noise or interference · CPC title