Multilayer wiring substrate

Patent metadata

Field	Value
Publication number	US-10959327-B2
Application number	US-201916412489-A
Country	US
Kind code	B2
Filing date	May 15, 2019
Priority date	Dec 2, 2016
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A plate-shaped multilayer wiring substrate includes at least two resin layers stacked on top of each other and each including an insulating base and a conductive pattern provided on the insulating base, and a front surface layer joined onto the resin layers stacked. The front surface layer has a higher elastic modulus than an elastic modulus of the insulating bases. A joint interface between the resin layers and the front surface layer includes projections and depressions. Also, a method for manufacturing the plate-shaped multilayer wiring substrate includes a step of stacking, on top of resin layers, a front surface layer having a higher elastic modulus than an elastic modulus of the resin layers, and a step of performing pressing under pressure from above the front surface layer by using a flat surface in a heated state to join the resin layers and the front surface layer.

First claim

What is claimed is:

1. A multilayer wiring substrate comprising:
at least two resin layers stacked on top of each other, each of the at least two resin layers including an insulating base and a conductive pattern provided on the insulating base;
a front surface layer joined onto the at least two resin layers, the front surface layer having a higher elastic modulus than an elastic modulus of the insulating bases; and
a protective film provided on the front surface layer; wherein
the multilayer wiring substrate is plate-shaped;
a joint interface between the at least two resin layers and the front surface layer includes projections and depressions;
an upper surface of the front surface layer is flat or substantially flat;
a surface conductor is provided on the front surface layer; and
a roughness of an interface between the front surface layer and the protective film is smaller than a roughness of the joint interface between the at least two resin layers and the front surface layer.

2. The multilayer wiring substrate according to claim 1 , wherein the front surface layer contains a glass filler.

3. The multilayer wiring substrate according to claim 2 , wherein a particle diameter of the glass filler is smaller than height difference between the projections and the depressions on the joint interface.

4. The multilayer wiring substrate according to claim 3 , wherein a portion of the glass filler is disposed in the depressions on the joint interface.

5. The multilayer wiring substrate according to claim 3 , wherein the glass filler is entirely disposed in the depressions on the joint interface.

6. The multilayer wiring substrate according to claim 2 , wherein a particle diameter of the glass filler is smaller than a film thickness of the conductive patterns.

7. The multilayer wiring substrate according to claim 2 , wherein a particle diameter of the glass filler is equal to or less than about one-third of a smaller of a height difference between the projections and the depressions on the joint interface and a film thickness of the conductive patterns.

8. The multilayer wiring substrate according to claim 2 , wherein the glass filler is also provided in a thinnest portion of the front surface layer.

9. The multilayer wiring substrate according to claim 2 , wherein the glass filler has a bimodal particle diameter distribution.

10. The multilayer wiring substrate according to claim 1 , wherein the front surface layer is made of a thermosetting resin.

11. The multilayer wiring substrate according to claim 10 , wherein the thermosetting resin is an epoxy resin.

12. The multilayer wiring substrate according to claim 2 , wherein the glass filler is glass fiber.

13. The multilayer wiring substrate according to claim 1 , wherein the at least two resin layers are made of a thermoplastic resin.

14. The multilayer wiring substrate according to claim 1 , wherein
the at least two resin layers further include an interlayer connection conductor passing through the insulating bases and containing a resin component; and
the front surface layer further includes an interlayer connection conductor passing through the front surface layer and containing no resin component.

15. The multilayer wiring substrate according to claim 1 , wherein the surface conductor has a film thickness larger than a film thickness of the conductive patterns included in the at least two resin layers and is provided on a surface of the front surface layer opposite to the joint interface.

16. The multilayer wiring substrate according to claim 1 , wherein a back surface layer having a higher elastic modulus than of an elastic modulus of the insulating bases is joined onto a surface of the at least two resin layers opposite to the joint interface.

17. The multilayer wiring substrate according to claim 16 , wherein a joint interface between the back surface layer and the at least two resin layers includes projections and depressions.

18. The multilayer wiring substrate according to claim 16 , wherein the front surface layer is made of a material identical to a material of the back surface layer.

19. The multilayer wiring substrate according to claim 16 , wherein the at least two resin layers include a first portion joined to the front surface layer or to the back surface layer, and a second portion that is not joined to either of the front surface layer or the back surface layer.

20. The multilayer wiring substrate according to claim 19 , wherein the second portion is bent.

21. The multilayer wiring substrate according to claim 1 , further comprising a mount component electrically connected to the conductive patterns.

Assignees

• Murata Manufacturing Co

Inventors

• Araki Shinichi
• Taguchi Hideyuki
• Noma Hayato
• Takada Ryosuke

Classifications

• H05K3/4688 Primary

  Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602) · CPC title

• H05K3/46

  Manufacturing multilayer circuits · CPC title

• H05K2201/0195

  Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure · CPC title

• H05K2201/0129

  Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer · CPC title

• H05K2201/0133

  Elastomeric or compliant polymer · CPC title