Deeply integrated voltage regulator architectures

Patent metadata

Field	Value
Publication number	US-10958172-B2
Application number	US-201916727909-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Dec 26, 2018
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

First claim

What is claimed is:

1. A system comprising:
a substrate;
a first chip on the substrate, wherein a load circuit is integrated on the first chip; and
a second chip on the substrate,
wherein a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node, wherein the power delivery circuit comprises:
a first circuit configured to generate an error signal based at least in part on the regulated voltage, and
a voltage generator comprising power switches configured to modify the regulated voltage according to the error signal,

wherein the first circuit of the power delivery circuit is integrated on the first chip, and
wherein at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

2. The system of claim 1 , wherein the error signal represents a difference between the regulated voltage at the node and a reference voltage.

3. The system of claim 2 , wherein the error signal comprises a series of pulses, and wherein a frequency of the series of pulses is based on the difference.

4. The system of claim 1 , wherein the error signal is an analog voltage.

5. The system of claim 1 , wherein the error signal is a digital value.

6. The system of claim 1 , wherein the error signal represents a difference between the regulated voltage at the node and a reference voltage multiplied by again factor.

7. The system of claim 1 , wherein the first circuit comprises an analog-to-digital converter configured to generate the error signal.

8. The system of claim 1 , wherein the power delivery circuit comprises a capacitor connected to the load circuit, wherein the capacitor is integrated on the first chip.

9. The system of claim 1 , wherein the power delivery circuit comprises one or more inductors connected to the load circuit, wherein the inductors are formed on the substrate separate from the first and second chips.

10. The system of claim 1 , wherein all of the power switches of the power delivery circuit are integrated on the second chip.

11. The system of claim 1 , further comprising a reference voltage generator configured to generate a reference voltage, wherein the error signal represents a difference between the regulated voltage at the node and the reference voltage and wherein the reference voltage generators integrated on the first chip.

12. The system of claim 1 , wherein the power delivery circuit comprises:
a capacitor connected to the load circuit; and
one or more inductors connected to the load circuit,
wherein the power switches, the capacitor, and the one or more inductors collectively form a voltage regulator.

13. The system of claim 12 , wherein the voltage regulator is multiphase.

14. A method of forming a system, the method comprising:
attaching a first chip to a substrate, wherein a load circuit is integrated on the first chip; and
attaching a second chip to the substrate,
wherein a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node, wherein the power delivery circuit comprises:
a first circuit configured to generate an error signal based at least in part on the regulated voltage, and
a voltage generator comprising power switches configured to modify the regulated voltage according to the error signal,

wherein the first circuit of the power delivery circuit is integrated on the first chip, and
wherein at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

15. The method of claim 14 , wherein the error signal represents a difference between the regulated voltage at the node and a reference voltage.

16. The method of claim 15 , wherein the error signal comprises a series of pulses, and wherein a frequency of the series of pulses is based on the difference.

17. The method of claim 14 , wherein the error signal is an analog voltage.

18. The method of claim 14 , wherein the error signal is a digital value.

19. The method of claim 14 , wherein the error signal represents a difference between the regulated voltage at the node and a reference voltage multiplied by again factor.

20. The method of claim 14 , wherein the first circuit comprises an analog-to-digital converter configured to generate the error signal.

21. The method of claim 14 , wherein the power delivery circuit comprises a capacitor connected to the load circuit, wherein the capacitor is integrated on the first chip.

22. The method of claim 14 , wherein the power delivery circuit comprises one or more inductors connected to the load circuit, wherein the inductors are formed on the substrate separate from the first and second chips.

23. The method of claim 14 , wherein all of the power switches of the power delivery circuit are integrated on the second chip.

24. The method of claim 14 , further comprising a reference voltage generator configured to generate a reference voltage, wherein the error signal represents a difference between the regulated voltage at the node and the reference voltage and wherein the reference voltage generators integrated on the first chip.

25. The method of claim 14 , wherein the power delivery circuit comprises:
a capacitor connected to the load circuit; and
one or more inductors connected to the load circuit,
wherein the power switches, the capacitor, and the one or more inductors collectively form a voltage regulator.

26. The method of claim 25 , wherein the voltage regulator is multiphase.

Assignees

• Empower Semiconductor Inc

Inventors

• Lidsky David

Classifications

• H02M7/4837

  Flying capacitor converters · CPC title

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title