Parallel voltage and current multiple amplitude shift key demodulation

Patent metadata

Field	Value
Publication number	US-10958110-B2
Application number	US-202016885247-A
Country	US
Kind code	B2
Filing date	May 27, 2020
Priority date	May 28, 2019
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

Systems, methods and apparatus for wireless charging are disclosed. A method for decoding data includes demodulating voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit, capturing a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a direct memory access (DMA) circuit, streaming bit sequences received from the DMA circuit into a plurality of data streams, and decoding one or more messages from the plurality of data streams.

First claim

What is claimed is:

1. A method for decoding data, comprising:
demodulating a voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit;
capturing a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a direct memory access (DMA) circuit;
streaming bit sequences received from the DMA circuit into a plurality of data streams; and
decoding one or more messages from the plurality of data streams.

2. The method of claim 1 , further comprising:
demodulating a voltage waveform in a first tank circuit to obtain a first demodulated signal; and
demodulating a current waveform in the first tank circuit to obtain a second demodulated signal.

3. The method of claim 2 , further comprising:
capturing a first bitstream that includes bits representing the first demodulated signal by clocking signal state of the first demodulated signal through the DMA circuit;
capturing a second bitstream that includes bits representing the second demodulated signal by clocking signal state of the second demodulated signal through the DMA circuit;
decoding the first bitstream and the second bitstream independently to obtain two versions of a first encoded message; and
selecting between the two versions of a first encoded message to provide one of the one or more messages decoded from the plurality of data streams.

4. The method of claim 2 , further comprising:
capturing a combined bitstream by clocking bits representing a combined signal state of the first demodulated signal and the second demodulated signal through the DMA circuit; and
decoding the combined bitstream to provide one of the one or more messages decoded from the plurality of data streams.

5. The method of claim 1 , wherein capturing the bit sequence from each demodulated signal comprises:
receiving a first demodulated signal at a first input of a general-purpose input/output (GPIO) port; and
receiving a second demodulated signal at a second input of the GPIO port.

6. The method of claim 5 , wherein the first demodulated signal is obtained from a first inductive power transfer circuit, and wherein the second demodulated signal is obtained from a second inductive power transfer circuit.

7. The method of claim 5 , wherein the first demodulated signal is obtained from a voltage waveform in a tank circuit of a first inductive power transfer circuit, and wherein the second demodulated signal is obtained from a current waveform in the tank circuit of the first inductive power transfer circuit.

8. The method of claim 5 , wherein the tank circuit of each inductive power transfer circuit comprises a charging coil and a capacitor.

9. A charging device, comprising:
a charging circuit that includes a plurality of inductive power transfer circuits, each inductive power transfer circuits having a charging coil located proximate to a surface of the charging device;
a direct memory access (DMA) circuit configured to receive at least one demodulated signal from each inductive power transfer circuit, wherein the at least one demodulated signal is obtained from a voltage or current waveform in a tank circuit of a corresponding inductive power transfer circuit; and
a controller configured to:
capture a bit sequence from each demodulated signal by clocking signal state of the each demodulated signal through the DMA circuit;
stream bit sequences received from the DMA circuit into a plurality of data streams; and
decode one or more messages from the plurality of data streams.

10. The charging device of claim 9 , wherein each inductive power transfer circuit comprises:
a tank circuit that includes a capacitor and a charging coil, wherein a first demodulated signal is obtained from a first inductive power transfer circuit by demodulating a voltage waveform in a corresponding first tank circuit, and wherein a second demodulated signal is obtained from the first inductive power transfer circuit by demodulating a current waveform in the first tank circuit.

11. The charging device of claim 10 , wherein the controller is further configured to:
capture a first bitstream that includes bits representing the first demodulated signal by clocking signal state of the first demodulated signal through the DMA circuit;
capture a second bitstream that includes bits representing the second demodulated signal by clocking signal state of the second demodulated signal through the DMA circuit;
decode the first bitstream and the second bitstream independently to obtain two versions of a first encoded message; and
select between the two versions of a first encoded message to provide one of the one or more messages decoded from the plurality of data streams.

12. The charging device of claim 10 , wherein the controller is further configured to:
capture a combined bitstream by clocking bits representing combined signal state of the first demodulated signal and the second demodulated signal through the DMA circuit; and
decode the combined bitstream to provide one of the one or more messages decoded from the plurality of data streams.

13. The charging device of claim 9 , wherein the controller is further configured to:
receive a first demodulated signal at a first input of a general-purpose input/output (GPIO) port; and
receiving a second demodulated signal at a second input of the GPIO port.

14. The charging device of claim 13 , wherein the first demodulated signal is obtained from a first inductive power transfer circuit, and wherein the second demodulated signal is obtained from a second inductive power transfer circuit.

15. The charging device of claim 13 , wherein the first demodulated signal is obtained from a voltage waveform in a tank circuit of a first inductive power transfer circuit, and wherein the second demodulated signal is obtained from a current waveform in the tank circuit of the first inductive power transfer circuit.

16. A non-transitory processor-readable storage medium comprising code for:
demodulating a voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit;
capturing a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a direct memory access (DMA) circuit;
streaming bit sequences received from the DMA circuit into a plurality of data streams; and
decoding one or more messages from the plurality of data streams.

17. A non-transitory processor-readable storage medium of claim 16 , further comprising code for:
demodulating a voltage waveform in a first tank circuit to obtain a first demodulated signal; and
demodulating a current waveform in the first tank circuit to obtain a second demodulated signal.

18. A non-transitory processor-readable storage medium of claim 17 , further comprising code for:
capturing a first bitstream that includes bits representing the first demodulated signal by clocking signal state of the first demodulated signal through the DMA circuit;
capturing a second bitstream that includes bits representing the second demodulated signal by clocking signal state of the second demodulated signal through the DMA circuit;
decoding the first bitstream and the second bitstream independently to obtain two versions of a first encoded message; and
selecting between the two versions of a first encoded message to provide one of the one or more messages decoded from the pluralit

Assignees

• Aira Inc

Inventors

• Goodchild Eric Heindel
• Winters John

Classifications

• H02J7/42

  with electronic devices having internal batteries, e.g. mobile phones · CPC title

• H02J50/80 Primary

  involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H02J50/402

  the two or more transmitting or the two or more receiving devices being integrated in the same unit, e.g. power mats with several coils or antennas with several sub-antennas · CPC title

• H02J50/12 Primary

  of the resonant type · CPC title