Semiconductor device including an integrated resistor and method of producing thereof

Patent metadata

Field	Value
Publication number	US-10957686-B2
Application number	US-202016744693-A
Country	US
Kind code	B2
Filing date	Jan 16, 2020
Priority date	Oct 25, 2016
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a transistor device in a semiconductor die including a semiconductor body, the transistor device comprising transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body;
a control terminal contact area at the first surface and electrically connected to a control electrode of each of the transistor cells;
a first load terminal contact area at the first surface and electrically connected to a first load terminal region of each of the transistor cells;
a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, wherein a current path from the control terminal contact area via the resistor to the first load terminal contact area is configured to discharge a gate of the transistor device at a failure mode of interruption of gate voltage supply; and
a pn junction diode in the semiconductor die and electrically connected in series with the resistor,
wherein at least one of the resistor and the pn junction diode laterally extends below the first load terminal contact area,
wherein the resistor is electrically connected to the first load terminal contact area via a contact.

2. The semiconductor device of claim 1 , wherein the pn junction diode and the resistor are included in a same semiconductor layer.

3. The semiconductor device of claim 2 , wherein the semiconductor layer extends from below the first load terminal contact area to below the control terminal contact area.

4. The semiconductor device of claim 2 , wherein the semiconductor layer extends from below the first load terminal contact area to below a control terminal interconnection line.

5. The semiconductor device of claim 4 , wherein the control terminal interconnection line includes a gate runner partly surrounding the active area, and wherein the semiconductor layer extends from below the first load terminal contact area to below the gate runner.

6. The semiconductor device of claim 2 , wherein the semiconductor layer is arranged in a trench which extends from below the first load terminal contact area to below the control terminal contact area.

7. The semiconductor device of claim 6 , wherein a dielectric structure in the trench electrically insulates the semiconductor layer including the resistor and the pn junction diode from a surrounding part of the semiconductor body.

8. The semiconductor device of claim 2 , wherein the semiconductor layer extends below the first load terminal contact area and/or the control terminal contact area and/or a control terminal interconnection line, and wherein the semiconductor layer is electrically connected to a respective one of the first load terminal contact area, the control terminal contact area, or the control terminal interconnection line by the contact.

9. The semiconductor device of claim 2 , wherein the resistor includes a serial connection of sub-resistors, wherein the pn junction diode includes a serial connection of sub-diodes, and wherein a location of the contact along an extension of the semiconductor layer in an extension area determines a resistance value of the resistor and a blocking voltage capability of the pn junction diode.

10. The semiconductor device of claim 1 , wherein the active area is surrounded by an edge termination area.

11. The semiconductor device of claim 1 , further comprising a second load terminal contact area at a second surface opposite to the first surface.

12. A method of producing a semiconductor device, the method comprising:
forming a transistor device in a semiconductor die including a semiconductor body, the transistor device comprising transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body;
forming a control terminal contact area at the first surface and electrically connected to a control electrode of each of the transistor cells;
forming a first load terminal contact area at the first surface and electrically connected to a first load terminal region of each of the transistor cells;
forming a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, wherein a current path from the control terminal contact area via the resistor to the first load terminal contact area is configured to discharge a gate of the transistor device at a failure mode of interruption of gate voltage supply; and
forming a pn junction diode electrically connected in series with the resistor,
wherein at least one of the resistor and the pn junction diode laterally extends below the first load terminal contact area,
wherein the resistor is electrically connected to the first load terminal contact area via a contact.

13. The method of claim 12 , wherein forming the pn junction diode comprises forming the pn junction diode in a same semiconductor layer as the resistor.

14. The method of claim 13 , wherein the semiconductor layer extends from below the first load terminal contact area to below the control terminal contact area.

15. The method of claim 13 , wherein the semiconductor layer extends from below the first load terminal contact area to below a control terminal interconnection line.

16. The method of claim 15 , wherein the control terminal interconnection line includes a gate runner partly surrounding the active area, and wherein the semiconductor layer extends from below the first load terminal contact area to below the gate runner.

17. The method of claim 13 , wherein forming the pn junction diode in the same semiconductor layer as the resistor comprises arranging the semiconductor layer in a trench that extends from below the first load terminal contact area to below the control terminal contact area.

18. The method of claim 17 , further comprising:
forming a dielectric structure in the trench and which electrically insulates the semiconductor layer including the resistor and the pn junction diode from a surrounding part of the semiconductor body.

19. The method of claim 13 , wherein the semiconductor layer extends below the first load terminal contact area and/or the control terminal contact area, the method further comprising:
electrically connecting the semiconductor layer to a respective one of the first load terminal contact area or the control terminal contact area by the contact.

20. The method of claim 13 , wherein forming the resistor comprises forming a serial connection of sub-resistors, wherein forming the pn junction diode comprises forming a serial connection of sub-diodes, the method further comprising:
selecting a location of the contact along an extension of the semiconductor layer in an extension area to determine a resistance value of the resistor and a blocking voltage capability of the pn junction diode.

Assignees

• Infineon Technologies Ag

Inventors

• Ahlers Dirk
• Zundel Markus
• Brandl Peter
• Matoy Kurt
• Ostermann Thomas

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/831

  Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202) · CPC title

• H10D12/441 Primary

  Vertical IGBTs · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title