Stable nickel silicide formation with fluorine incorporation and related IC structure
US-9379207-B2 · Jun 28, 2016 · US
US10586792B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10586792-B2 |
| Application number | US-201816236741-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 31, 2018 |
| Priority date | Oct 25, 2016 |
| Publication date | Mar 10, 2020 |
| Grant date | Mar 10, 2020 |
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A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a transistor device in a semiconductor die including a semiconductor body, the transistor device comprising transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body; a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells; a first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells; and a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, wherein a current path from the control terminal contact area via the resistor first load terminal contact area is configured to discharge a gate of the transitor device at a failure mode of interruption of the gate voltage supply; and a pn junction diode electrically coneected in series with the resistor, wherein the resistor or the pn junction diode laterally extends between the control terminal contact area or below a control terminal interconnection line and the first load terminal contact area, wherein the resistor is electrically connected to the control terminal contact area or the control terminal interconnection line via a contact, wherein an electrical resistance of the resistor is set by a position of the contact along a lateral extension of the resistor below the control terminal contact area or below the control terminal interconnection line. 2. The semiconductor device of claim 1 , further comprising a single metal wiring level, wherein the control terminal contact area and the first load terminal contact area are different parts of the single metal wiring level. 3. The semiconductor device of claim 1 , wherein the transistor device is an n-type channel IGFET and an anode of the pn junction diode is electrically coupled to the control terminal electrode. 4. The semiconductor device of claim 1 , wherein the pn junction diode is a polycrystalline silicon pn junction diode. 5. The semiconductor device of claim 1 , wherein the resistor and the pn junction diode constitute different parts of a single polycrystalline silicon wiring level, the polycrystalline silicon wiring level including parts of different conductivity type. 6. The semiconductor device of claim 1 , wherein a forward voltage VF of the diode structure at a forward current in a range of 1 mA and 10 mA is smaller than a threshold voltage of the transistor device at the same current level. 7. The semiconductor device of claim 1 , wherein the pn junction diode comprises a chain of pn junction sub-diodes electrically connected in series. 8. The semiconductor device of claim 1 , wherein the resistor is at least partly embedded in an intermediate dielectric sandwiched between a wiring level of the first load terminal contact area and the first surface. 9. The semiconductor device of claim 1 , wherein the resistor is at least partly arranged in a trench and electrically insulated from a surrounding part of the semiconductor body by a trench dielectric. 10. The semiconductor device of claim 1 , wherein the transistor device is a vertical transistor device and further includes an edge termination area surrounding the active area, and a second load terminal contact area at a second surface opposite to the first surface. 11. The semiconductor device of claim 1 , wherein the pn junction diode laterally extends below the control terminal contact area or the control terminal interconnection line, and wherein the resistor laterally extends below the first load terminal contact area. 12. The semiconductor device of claim 1 , wherein the transistor device is a power transistor device of more than 1A rated maximum load current and a rated load terminal to load terminal breakdown voltage larger than 10V.
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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