Storage system with host-directed error scanning of solid-state storage devices

US10956245B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10956245-B1
Application numberUS-201715663443-A
CountryUS
Kind codeB1
Filing dateJul 28, 2017
Priority dateJul 28, 2017
Publication dateMar 23, 2021
Grant dateMar 23, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A storage system in one embodiment comprises a host processor, and a solid-state storage device coupled to the host processor and comprising a non-volatile memory and a storage controller. The host processor is configured to initiate an error scanning operation on a designated portion of the non-volatile memory by directing at least one read command to the storage controller. The read command is configured to indicate to the storage controller that data read from the non-volatile memory responsive to the read command is not to be returned to the host processor. For example, the read command may illustratively comprise a Scatter Gather List (SGL) bit bucket descriptor indicating that the data read from the non-volatile memory responsive to the read command is to be discarded rather than returned to the host processor. The storage controller records any detected errors in a media error log and notifies the host processor of such errors.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage system comprising: a host processor; and a solid-state storage device coupled to the host processor and comprising a non-volatile memory and a storage controller; wherein the host processor is configured to initiate an error scanning operation on a designated portion of the non-volatile memory by directing at least one read command to the storage controller; wherein the read command as generated by the host processor is configured to indicate to the storage controller that data read from the non-volatile memory responsive to the read command is not to be returned to the host processor regardless of whether or not the error scanning operation finds any errors; the data read from the non-volatile memory responsive to the read command thereby not being returned to the host processor even if no errors are detected in that data by the error scanning operation; wherein the host processor by issuing multiple read commands controls the performance of respective corresponding error scan operations on different portions of the non-volatile memory of the solid-state storage device; wherein said at least one read command comprises one or more of a force-media-access parameter that is set by the host processor to instruct the storage controller to retrieve all available data from the non-volatile memory for each of a plurality of designated logical blocks, and a limit-media-error-recovery parameter that is set by the host processor to instruct the storage controller to more aggressively identify marginal instances of logical blocks in the designated portion of the non-volatile memory; and wherein said at least one read command is configured by the host processor to instruct the storage controller to check available data integrity format protection information for the designated portion of the non-volatile memory. 2. The storage system of claim 1 wherein said at least one read command identifies as the designated portion of the non-volatile memory subject to the error scanning operation a particular set of logical block addresses that designate one or more portions of the non-volatile memory. 3. The storage system of claim 1 wherein the designated portion of the non-volatile memory subject to the error scanning operation comprises a portion of the non-volatile memory that is determined by the host processor to contain data of a higher importance level or a greater value than data contained in other portions of the non-volatile memory. 4. The storage system of claim 1 wherein the designated portion of the non-volatile memory subject to the error scanning operation comprises one or more portions of the non-volatile memory that are each determined by the host processor to contain valid host data. 5. The storage system of claim 1 wherein said at least one read command comprises a Scatter Gather List (SGL) bit bucket descriptor indicating that the data read from the non-volatile memory responsive to the read command is to be discarded rather than returned to the host processor. 6. The storage system of claim 1 wherein the force-media-access parameter comprises a Force Unit Access (FUA) bit that is set by the host processor to a logic one value in the read command. 7. The storage system of claim 1 wherein the limit-media-error-recovery parameter comprises a Limited Retry (LR) bit that is set by the host processor to a logic one value in the read command. 8. The storage system of claim 1 wherein the host processor instructs the storage controller to check available data integrity format protection information by setting at least one of a Protection Information Check (PRCHK) field, an Initial Logical Block Reference Tag (ILBRT) field, a Logical Block Application Tag Mask (LBATM) field, and a Logical Block Application Tag (LBAT) field to respective designated values in the read command. 9. The storage system of claim 1 wherein the error scanning operation comprises performing error correction code checks on data stored in the designated portion of the non-volatile memory. 10. The storage system of claim 1 wherein for a given error detected as part of the error scanning operation, the storage controller is configured: to record information identifying a logical block containing the given error in a media error log; and to notify the host processor of the given error. 11. The storage system of claim 1 wherein the host processor is configured: to identify a period of relatively low host processor activity requiring minimal resources of the solid-state storage device; and to generate said at least one read command for the identified period. 12. The storage system of claim 1 wherein the host processor is configured to initiate at least one of the following operations responsive to an error notification from the storage controller relating to a particular logical block: to rewrite the logical block with data designated by the host processor; to recover the logical block using a higher-level host protection mechanism; and to instruct the storage controller to deallocate the logical block. 13. The storage system of claim 1 further comprising a PCIe switch having an upstream port coupled to a given one of a plurality of root ports of a PCIe root complex of the host processor and a downstream port coupled to the solid-state storage device. 14. A method comprising: generating at least one read command in a host processor of a storage system; and directing said at least one read command to a storage controller of a solid-state storage device of the storage system; wherein said at least one read command initiates an error scanning operation by the storage controller on a designated portion of a non-volatile memory of the solid-state storage device; wherein the read command as generated by the host processor is configured to indicate to the storage controller that data read from the non-volatile memory responsive to the read command is not to be returned to the host processor regardless of whether or not the error scanning operation finds any errors; the data read from the non-volatile memory responsive to the read command thereby not being returned to the host processor even if no errors are detected in that data by the error scanning operation; wherein the host processor by issuing multiple read commands controls the performance of respective corresponding error scan operations on different portions of the non-volatile memory of the solid-state storage device; wherein said at least one read command comprises one or more of a force-media-access parameter that is set by the host processor to instruct the storage controller to retrieve all available data from the non-volatile memory for each of a plurality of designated logical blocks, and a limit-media-error-recovery parameter that is set by the host processor to instruct the storage controller to more aggressively identify marginal instances of logical blocks in the designated portion of the non-volatile memory; and wherein said at least one read command is configured by the host processor to instruct the storage controller to check available data integrity format protection information for the designated portion of the non-volatile memory. 15. The method of claim 14 wherein said at least one read command comprises a Scatter Gather List (SGL) bit bucket descriptor indicating that the data read from the non-volatile memory responsive to the read command is to be discarded rather than returned to the host processor. 16. A computer program product comprising a non-transitory processor-readable storage medium having store

Assignees

Inventors

Classifications

  • Correcting systematically all correctable errors, i.e. scrubbing · CPC title

  • G06F3/0616Primary

    in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • Management of blocks · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

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What does patent US10956245B1 cover?
A storage system in one embodiment comprises a host processor, and a solid-state storage device coupled to the host processor and comprising a non-volatile memory and a storage controller. The host processor is configured to initiate an error scanning operation on a designated portion of the non-volatile memory by directing at least one read command to the storage controller. The read command i…
Who is the assignee on this patent?
Emc Ip Holding Co Llc
What technology area does this patent fall under?
Primary CPC classification G06F3/0616. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 23 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).