Hybrid solid state drive (ssd) using pcm or other high performance solid-state memory

Patent metadata

Field	Value
Publication number	US-2016239205-A1
Application number	US-201514620971-A
Country	US
Kind code	A1
Filing date	Feb 12, 2015
Priority date	Feb 12, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

Techniques for implementing a hybrid non-volatile memory storage system are disclosed. The hybrid memory system may include a first non-volatile memory; a second non-volatile memory; and a memory controller to analyze a type of an operation and a characteristic of the operation, to determine a state of the second non-volatile memory, and to determine whether another operation is being implemented on the second non-volatile memory, the memory controller selectively implementing an operation on one of the first non-volatile memory and the second non-volatile memory segment based on the type of the operation, the characteristic of the operation, the state of the second non-volatile memory, and whether another operation is being implemented on the second non-volatile memory such that the memory controller implements the operation on the first non-volatile memory concurrently with the other operation being implemented on the second non-volatile memory based on the type of the operation.

First claim

What is claimed is:

1 . A hybrid memory system comprising:
a first non-volatile memory, the first non-volatile memory being a first type of non-volatile memory; a second non-volatile memory, the second non-volatile memory being a second type of non-volatile memory different from the first type of non-volatile memory; and a memory controller configured to analyze a type of the operation and a characteristic of the operation, to determine a state of the second non-volatile memory, and to determine whether another operation is being implemented on the second non-volatile memory, the memory controller being further configured to selectively implement an operation on one of the first non-volatile memory and the second non-volatile memory segment based on the type of the operation, the characteristic of the operation, the state of the second non-volatile memory, and whether another operation is being implemented on the second non-volatile memory, wherein the memory controller is configured implement the operation on the first non-volatile memory concurrently with the other operation being implemented on the second non-volatile memory based on the type of the operation.

2 . The hybrid memory system of claim 1 , wherein the first non-volatile memory and the second non-volatile memory are within a single solid state drive.

3 . The hybrid memory system of claim 1 , wherein the first non-volatile memory is one of a memristor, ReRam, and phase-change memory (PCM).

4 . The hybrid memory system of claim 1 , wherein the second non-volatile memory is NAND flash memory.

5 . The hybrid memory system of claim 1 , wherein a size of the first non-volatile memory is smaller than a size of the second non-volatile memory.

6 . The hybrid memory system of claim 1 , wherein the operation is a host operation.

7 . The hybrid memory system of claim 6 , wherein the host operation is one of a read operation, a write operation, and an erase operation.

8 . The hybrid memory system of claim 7 , wherein the other operation is a background operation.

9 . The hybrid memory system of claim 8 , wherein the background operation is one of a background scan, background erase, PLI self test, system data save, system area refresh, background data refresh, background defrag, wear leveling, garbage collection, read disturb data relocation, background media scan, temperature check, flush logs to disk, update drive usage log, and boot flash check.

10 . The hybrid memory system of claim 1 , wherein the memory controller is configured to analyze the operation to determine whether it is a host operation or a background operation.

11 . The hybrid memory system of claim 10 , wherein when it is determined that the host operation is a write operation, the memory controller is configured to cache data corresponding to the write operation to the first non-volatile memory.

12 . The hybrid memory system of claim 10 , wherein when it is determined that the host operation is a read operation, the memory controller is configured to read data corresponding to read operation from the second non-volatile memory.

13 . The hybrid memory system of claim 1 , wherein the characteristic of the operation is an amount of data associated with the operation.

14 . The hybrid memory system of claim 13 , wherein when the amount of data associated with the operation is less than a predetermined threshold and the operation is a write operation, the memory controller caches the data associated the write operation on the first non-volatile memory.

15 . The hybrid memory system of claim 1 , wherein the state of the second non-volatile memory is one of busy and idle.

16 . The hybrid memory system of claim 15 , wherein when the state is busy, the memory controller implements the operation on the first non-volatile memory, and when the state is idle, the memory controller implements the operation on the first non-volatile memory when the type of operation is a first type and the second non-volatile memory when the type of the operation is a second type.

17 . The hybrid memory system of claim 1 , wherein the memory controller is configured to queue the operation based on the state of the second non-volatile memory.

18 . The hybrid memory system of claim 17 , wherein the operation is queued for implementation on the second non-volatile memory based on the type of the operation.

19 . A computer program product comprised of a series of instructions executable on a computer, the computer program product performing a process for implementing a hybrid memory system; the computer program implementing the steps of:
storing first data in a first non-volatile memory; storing second data a second non-volatile memory different from the first non-volatile memory; analyzing a type of the operation and a characteristic of the operation; determining a state of the second non-volatile memory; determining whether another operation is being implemented on the second non-volatile memory; and selectively implementing an operation on one of the first non-volatile memory and the second non-volatile memory segment based on the type of the operation, the characteristic of the operation, the state of the second non-volatile memory and whether another operation is being implemented on the second non-volatile memory, wherein the operation is implemented on the first non-volatile memory concurrently with the other operation being implemented on the second non-volatile memory based on the type of the operation.

20 . A method for implementing a hybrid memory system comprising:
storing first data in a first non-volatile memory; storing second data a second non-volatile memory different from the first non-volatile memory; analyzing a type of the operation and a characteristic of the operation; determining a state of the second non-volatile memory; determining whether another operation is being implemented on the second non-volatile memory; and selectively implementing an operation on one of the first non-volatile memory and the second non-volatile memory segment based on the type of the operation, the characteristic of the operation, the state of the second non-volatile memory and whether another operation is being implemented on the second non-volatile memory, wherein the operation is implemented on the first non-volatile memory concurrently with the other operation being implemented on the second non-volatile memory based on the type of the operation.

Assignees

• HGST Netherlands BV

Inventors

• Rothberg Michael Stephen

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title