Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment

Patent metadata

Field	Value
Publication number	US-10956148-B2
Application number	US-201916684328-A
Country	US
Kind code	B2
Filing date	Nov 14, 2019
Priority date	Dec 8, 2016
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

First claim

What is claimed is:

1. A computer program product, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by at least one processor for a code load management engine to perform:
performing, with the code load management engine, concurrent code activation for a first set of Input/Output (I/O) enclosures by:
sending, with the code load management engine, first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein each I/O enclosure management engine sets a flag for each I/O enclosure in the first set of I/O enclosures to indicate that the I/O enclosure is undergoing code activation;
activating, with the code load management engine, an update image on the first set of I/O enclosures by sending an activate reset command to each of the first set of I/O enclosures, wherein, in response to receiving the activate reset command, firmware of each I/O enclosure in the first set of I/O enclosures starts an Field-Programmable Gate Array (FPGA) reset process to reprogram the FPGA; and
sending, with the code load management engine, second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed, wherein each I/O enclosure management engine clears the flag for each I/O enclosure in the first set of I/O enclosures to indicate that the code activation is completed; and

performing, with the code load management engine, concurrent code activation for a second set of I/O enclosures.

2. The computer program product of claim 1 , wherein the program code is executable by at least one processor to perform:
performing, with the code load management engine, high-level system pre-checks on the first set of I/O enclosures and the second set of I/O enclosures.

3. The computer program product of claim 1 , wherein the program code is executable by at least one processor to perform:
activating, with the code load management engine, the update image on the second set of I/O enclosures.

4. The computer program product of claim 1 , wherein, in response to receiving the activate reset command, a new firmware image is loaded into a processor module of each I/O enclosure in the first set of I/O enclosures.

5. The computer program product of claim 1 , wherein the plurality of server nodes are coupled to a computer system storing the code load management engine, and wherein the plurality of server nodes and the computer system comprise nodes in a cloud infrastructure.

6. A computer system, comprising:
a code load management engine;
one or more processors, one or more computer-readable memories and one or more computer-readable, tangible storage devices; and
program instructions, stored on at least one of the one or more computer-readable, tangible storage devices executed by at least one of the one or more processors via at least one of the one or more computer-readable memories, to perform operations comprising:
performing, with the code load management engine, concurrent code activation for a first set of Input/Output (I/O) enclosures by:
sending, with the code load management engine, first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein each I/O enclosure management engine sets a flag for each I/O enclosure in the first set of I/O enclosures to indicate that the I/O enclosure is undergoing code activation;
activating, with the code load management engine, an update image on the first set of I/O enclosures by sending an activate reset command to each of the first set of I/O enclosures, wherein, in response to receiving the activate reset command, firmware of each I/O enclosure in the first set of I/O enclosures starts an Field-Programmable Gate Array (FPGA) reset process to reprogram the FPGA; and
sending, with the code load management engine, second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed, wherein each I/O enclosure management engine clears the flag for each I/O enclosure in the first set of I/O enclosures to indicate that the code activation is completed; and

performing, with the code load management engine, concurrent code activation for a second set of I/O enclosures.

7. The computer system of claim 6 , wherein the operations further comprise:
performing, with the code load management engine, high-level system pre-checks on the first set of I/O enclosures and the second set of I/O enclosures.

8. The computer system of claim 7 , wherein the operations further comprise:
activating, with the code load management engine, the update image on the second set of I/O enclosures.

9. The computer system of claim 7 , wherein, in response to receiving the activate reset command, a new firmware image is loaded into a processor module of each I/O enclosure in the first set of I/O enclosures.

10. The computer system of claim 7 , wherein the plurality of server nodes are coupled to the computer system storing the code load management engine, and wherein the plurality of server nodes and the computer system comprise nodes in a cloud infrastructure.

11. A method implemented in a computer system, comprising:
performing, with a code load management engine, concurrent code activation for a first set of Input/Output (I/O) enclosures by:
sending, with the code load management engine, first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein each I/O enclosure management engine sets a flag for each I/O enclosure in the first set of I/O enclosures to indicate that the I/O enclosure is undergoing code activation;
activating, with the code load management engine, an update image on the first set of I/O enclosures by sending an activate reset command to each of the first set of I/O enclosures, wherein, in response to receiving the activate reset command, firmware of each I/O enclosure in the first set of I/O enclosures starts an Field-Programmable Gate Array (FPGA) reset process to reprogram the FPGA; and
sending, with the code load management engine, second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed, wherein each I/O enclosure management engine clears the flag for each I/O enclosure in the first set of I/O enclosures to indicate that the code activation is completed; and

performing, with the code load management engine, concurrent code activation for a second set of I/O enclosures.

12. The method implemented in the computer system of claim 11 , further comprising:
performing, with the code load management engine, high-level system pre-checks on the first set of I/O enclosures and the second set of I/O enclosures.

13. The method implemented in the computer system of claim 11 , further comprising:
activating, with the code load management engine, the update image on the second set of I/O enclosures.

14. The method implemented in the computer system of claim 11 , wherein, in response to receiving the activate reset command, a new firmware image is loaded into a processor module of each I/O enclosure in the first set of I/O enclosures.

15. The method implemented in t

Assignees

• IBM

Inventors

• Batchelor Gary W
• Davila Veronica S
• Garcia Enrique Q
• Han Robin
• Kirch Jay T
• Martens Ronald D
• Nguyen Trung N
• Rinaldi Brian A
• Sorenson Todd C

Classifications

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title

• H04L67/34

  involving the movement of software or configuration parameters  (network booting or remote initial program loading [RIPL] G06F9/4416) · CPC title

• H04L67/10

  in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) · CPC title