Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment

Patent metadata

Field	Value
Publication number	US-10114633-B2
Application number	US-201615373116-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Dec 8, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

First claim

What is claimed is:

1. A computer program product, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by at least one processor to perform:
dividing a plurality of I/O enclosures into a first set of I/O enclosures and a second set of I/O enclosures; and
performing concurrent code activation for the first set of I/O enclosures by:
sending first notifications to each Input/Output (I/O) enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored;
distributing an update image to the first set of I/O enclosures;
activating the update image on the first set of I/O enclosures by sending an activate reset command to each of the first set of I/O enclosures, wherein the activate reset command is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures; and
in response to the activate reset command completing on the first set of I/O enclosures,
sending second notifications to each I/O enclosure management engine on each of the server nodes that code activation for the first set of I/O enclosures has completed; and
performing concurrent code activation for the second set of I/O enclosures.

2. The computer program product of claim 1 , wherein the program code is executable by at least one processor to perform:
performing high-level system pre-checks to ensure that the first set of I/O enclosures and the second set of I/O enclosures are ready for code update.

3. The computer program product of claim 1 , wherein the program code is executable by at least one processor to perform:
distributing the update image to the second set of I/O enclosures; and
activating the update image on the second set of I/O enclosures.

4. The computer program product of claim 1 , wherein program code of an I/O enclosure management engine on a server node of the plurality of server nodes is executable by at least one processor to perform:
in response to receiving a first notification of the first notifications,
setting a flag for each of the first set of I/O enclosures; and
ignoring the errors that disrupt the code activation; and

in response to receiving a second notification of the second notifications, clearing the flag.

5. The computer program product of claim 1 , wherein program code of an I/O enclosure of the first set of I/O enclosures is executable by at least one processor to perform:
in response to firmware of the I/O enclosure receiving the activate reset command, starting a Field-Programmable Gate Array (FPGA) reset process.

6. The computer program product of claim 1 , wherein the plurality of server nodes are coupled to a computing system storing a code load management engine, and wherein the plurality of server nodes and the computing system comprise nodes in a cloud infrastructure.

7. A computer system, comprising:
one or more processors, one or more computer-readable memories and one or more computer-readable, tangible storage devices; and
program instructions, stored on at least one of the one or more computer-readable, tangible storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, to perform operations comprising:
dividing a plurality of I/O enclosures into a first set of I/O enclosures and a second set of I/O enclosures; and
performing concurrent code activation for the first set of I/O enclosures by:
sending first notifications to each Input/Output (I/O) enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored;
distributing an update image t the first set of I/O enclosures;
activating the update image on the first set of I/O enclosures by sending an activate reset command to each of the first set of I/O enclosures, wherein the activate reset command is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures; and
in response to the activate reset command completing on the first set of I/O enclosures,
sending second notifications to each I/O enclosure management engine on each of the server nodes that code activation for the first set of I/O enclosures has completed; and
performing concurrent code activation for the second set of I/O enclosures.

8. The computer system of claim 7 , wherein the operations further comprise:
performing high-level system pre-checks to ensure that the first set of I/O enclosures and the second set of I/O enclosures are ready for code update.

9. The computer system of claim 7 , wherein the operations further comprise:
distributing the update image to the second set of I/O enclosures; and
activating the update image on the second set of I/O enclosures.

10. The computer system of claim 7 , wherein the operations of an I/O enclosure management engine on a server node of the plurality of server nodes further comprise:
in response to receiving a first notification of the first notifications,
setting a flag for each of the first set of I/O enclosures; and
ignoring the errors that disrupt the code activation; and

in response to receiving a second notification of the second notifications, clearing the flag.

11. The computer system of claim 7 , wherein the operations of an I/O enclosure of the first set of I/O enclosures further comprise:
in response to firmware of the I/O enclosure receiving the activate reset command, starting a Field-Programmable Gate Array (FPGA) reset process.

12. The computer system of claim 7 , wherein the plurality of server nodes are coupled to a computing system storing a code load management engine, and wherein the plurality of server nodes and the computing system comprise nodes in a cloud infrastructure.

13. A method, comprising:
dividing, with a processor of a computing system, a plurality of I/O enclosures into a first set of I/O enclosures and a second set of I/O enclosures; and
performing, with the processor of the computing system, concurrent code activation for the first set of I/O enclosures by:
sending, with the processor of the computing system, first notifications to each Input/Output (I/O) enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored;
distributing, with the processor of the computing system, an update image to the first set of I/O enclosures;
activating, with the processor of the computing system, the update image on the first set of I/O enclosures by sending an activate reset command to each of the first set of I/O enclosures, wherein the activate reset command is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures; and
in response to the activate reset command completing on the first set of I/O enclosures,
sending second notifications to each I/O enclosure management engine on each of the server nodes that code activation for the first set of I/O enclosures has completed; and
performing concurrent code activation for the second set of I/O enclosures.

14. The method of claim 13 , further comprising:
performing, with the processor of the computing system, high-level system pre-checks to ensure that the first set of I/O enclosures and the second set of I/O enclosures are ready for code update.

15. The method of claim 1

Assignees

• IBM

Inventors

• Batchelor Gary W
• Davila Veronica S
• Garcia Enrique Q
• Han Robin
• Kirch Jay T
• Martens Ronald D
• Nguyen Trung N
• Rinaldi Brian A
• Sorenson Todd C

Classifications

• H04L67/34

  involving the movement of software or configuration parameters  (network booting or remote initial program loading [RIPL] G06F9/4416) · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title

• H04L67/10

  in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) · CPC title