Ceramic circuit board and semiconductor module

US10952317B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10952317-B2
Application numberUS-202016781741-A
CountryUS
Kind codeB2
Filing dateFeb 4, 2020
Priority dateJul 14, 2016
Publication dateMar 16, 2021
Grant dateMar 16, 2021

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A ceramic circuit board comprises: a ceramic substrate with a 1.0 mm thickness or less including a first surface and a second surface, the first surface including a first area and a second area; a first metal plate joined to the first area; and a second metal plate joined to the second surface. The second area has a first waviness profile along a first side of the first surface, the first waviness profile having one extreme value or less. The second area has a second waviness profile along a second side of the first surface, the second waviness profile has not less than two nor more than three extreme values.

First claim

Opening claim text (preview).

What is claimed is: 1. A ceramic circuit board comprising: a ceramic substrate with a 1.0 mm thickness or less, the substrate including a first surface and a second surface, the first surface including a first area and a second area; a first metal plate joined to the first area with a first joining layer therebetween; and a second metal plate joined to the second surface with a second joining layer therebetween, wherein the first surface extends along a first direction and a second direction across the first direction, wherein the second area has a first waviness profile along a first side in the first direction of the first surface, the first waviness profile having one extreme value or less, wherein the second area has a second waviness profile along a second side in the second direction of the first surface, the second waviness profile having not less than two nor more than three extreme values, wherein the first joining layer has a first protrusion provided on the first surface and extending from a first interface between the first joining layer and the first metal plate, the first protrusion has a length of 10 μm or more and 100 μm or less, and the first interface and a side surface of the first metal plate define a first angle of 80 degrees or less therebetween, and wherein the second joining layer has a second protrusion provided on the second surface and extending from a second interface between the second joining layer and the second metal plate, the second protrusion has a length of 10 μm or more and 100 μm or less, and the second interface and a side surface of the second metal plate define a second angle of 80 degrees or less therebetween. 2. The ceramic circuit board according to claim 1 , wherein the first waviness profile is substantially arc-shaped, and wherein the second waviness profile is substantially M-shaped or substantially S-shaped. 3. The ceramic circuit board according to claim 1 , wherein each of the first and second metal plates has a thickness of 0.6 mm or more. 4. The ceramic circuit board according to claim 1 , wherein a thickness of a metal plate having the largest thickness out of the first metal plate and the second metal plate is 1.5 times or less as large as the thickness of the ceramic substrate. 5. The ceramic circuit board according to claim 1 , wherein a length of the first side is 1.25 times or more as long as a length of the second side. 6. The ceramic circuit board according to claim 1 , wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.30 mm or less. 7. The ceramic circuit board according to claim 1 , wherein a difference between a maximum value and a minimum value of at least one profile selected from the group consisting of the first and second waviness profiles is 10 μm or more. 8. The ceramic circuit board according to claim 1 , further comprising a lead terminal with a 0.2 mm thickness or more, the lead terminal being joined to the first metal plate. 9. The ceramic circuit board according to claim 8 , wherein a difference between a maximum value and a minimum value of at least one profile selected from the group consisting of the first and second waviness profiles is 40 μm or less. 10. A semiconductor module comprising: the ceramic circuit board according to claim 8 ; a semiconductor element provided on the first metal plate; and a heat dissipation member provided on the second metal plate. 11. The ceramic circuit board according to claim 1 , wherein the first waviness profile is substantially arc-shaped, wherein the second waviness profile is substantially M-shaped or substantially S-shaped, wherein at least one plate selected from the group consisting of the first and second metal plates has a thickness of 0.6 mm or more, and wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.30 mm or less. 12. The ceramic circuit board according to claim 7 , wherein the first waviness profile is substantially arc-shaped, wherein the second waviness profile is substantially M-shaped or substantially S-shaped, wherein at least one plate selected from the group consisting of the first and second metal plates has a thickness of 0.6 mm or more, and wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.30 mm or less. 13. The semiconductor module according to claim 10 , wherein the first waviness profile is substantially arc-shaped, wherein the second waviness profile is substantially M-shaped or substantially S-shaped, wherein at least one plate selected from the group consisting of the first and second metal plates has a thickness of 0.6 mm or more, and wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.30 mm or less. 14. The ceramic circuit board according to claim 1 , wherein the second area has two of the second waviness profiles, each second waviness profile is substantially M-shaped. 15. The ceramic circuit board according to claim 1 , wherein the second area has two of the second waviness profiles, each second waviness profile is substantially S-shaped. 16. The ceramic circuit board according to claim 2 , wherein the second area has two of the second waviness profiles, each second waviness profile is substantially M-shaped. 17. The ceramic circuit board according to claim 2 , wherein the second area has two of the second waviness profiles, each second waviness profile is substantially S-shaped.

Assignees

Inventors

Classifications

  • Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

  • characterised by the interlayer used (C04B37/028 takes precedence) · CPC title

  • Ceramics or glasses · CPC title

  • H10W70/68Primary

    Shapes or dispositions thereof · CPC title

  • H10W40/255Primary

    having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

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What does patent US10952317B2 cover?
A ceramic circuit board comprises: a ceramic substrate with a 1.0 mm thickness or less including a first surface and a second surface, the first surface including a first area and a second area; a first metal plate joined to the first area; and a second metal plate joined to the second surface. The second area has a first waviness profile along a first side of the first surface, the first wavin…
Who is the assignee on this patent?
Toshiba Kk, Toshiba Materials Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/68. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).