Method for producing a plurality of optoelectronic components, and optoelectronic component

US10950746B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10950746-B2
Application numberUS-201816484553-A
CountryUS
Kind codeB2
Filing dateFeb 2, 2018
Priority dateFeb 15, 2017
Publication dateMar 16, 2021
Grant dateMar 16, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for producing a plurality of optoelectronic components are disclosed. In an embodiment, the method includes providing a substrate, epitaxially applying a sacrificial layer on the substrate, wherein the sacrificial layer has a layer thickness greater than 300 nm and comprises AlxGa(1-x)As with 0<x≤1, epitaxially applying a semiconductor layer sequence on the sacrificial layer, forming trenches extending in a vertical direction through the semiconductor layer sequence to the sacrificial layer such that a plurality of regions in the semiconductor layer sequence is formed and wet thermally oxidizing the sacrificial layer such that the substrate is non-destructively removable from the semiconductor layer sequence, wherein the sacrificial layer comprises at least three and optionally four sublayers in a direction facing away from the substrate, a first sublayer comprising InGaAlP, a second sublayer comprising GaAs, a third sublayer comprising AlxGa(1-x)As with 0<x≤1 and a fourth sublayer comprising GaAs.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of producing a plurality of optoelectronic components, the method comprising: providing a substrate; epitaxially applying a sacrificial layer on the substrate, wherein the sacrificial layer has a layer thickness greater than 300 nm, and wherein the sacrificial layer comprises Al x Ga (1-x) As with 0<x≤1; epitaxially applying a semiconductor layer sequence on the sacrificial layer; forming trenches extending in a vertical direction through the semiconductor layer sequence to the sacrificial layer such that a plurality of regions in the semiconductor layer sequence is formed; and wet thermally oxidizing the sacrificial layer such that the substrate is non-destructively removable from the semiconductor layer sequence, wherein the sacrificial layer comprises at least three and optionally four sublayers in a direction facing away from the substrate, a first sublayer comprising InGaAlP, a second sublayer comprising GaAs, a third sublayer comprising Al x Ga (1-x) As with 0<x≤1 and a fourth sublayer comprising GaAs. 2. The method according to claim 1 , further comprising applying an auxiliary carrier to a side of the semiconductor layer sequence opposite the substrate after forming trenches and after wet thermally oxidizing. 3. The method according to claim 2 , wherein the auxiliary carrier is a germanium carrier, a sapphire carrier, a plastic carrier or a silicon carrier. 4. The method according to claim 2 , further comprising: removing the auxiliary carrier and the semiconductor layer sequence from the substrate; and subsequently separating at least the auxiliary carrier so that the plurality of optoelectronic components is obtained. 5. The method according to claim 1 , wherein wet thermally oxidizing is carried out at a temperature of less than 400° C. under a steam atmosphere. 6. The method according to claim 1 , wherein wet thermally oxidizing comprises only partially oxidizing the sacrificial layer such that there are non-oxidized regions between the semiconductor layer sequence and the substrate comprises Al x Ga (1-x) As with x≤1. 7. The method according to claim 1 , wherein the first sublayer serves as a protective layer for the substrate and has a layer thickness of 1 nm to 350 nm, wherein the second sublayer has a layer thickness of 1 nm to 500 nm, and wherein the fourth sublayer serves as a protective layer for the semiconductor layer sequence and has a layer thickness of 1 nm to 120 nm. 8. The method according to claim 1 , wherein 0.95≤x<1, and wherein the layer thickness of the sacrificial layer is between 600 nm and 800 nm, inclusive. 9. The method according to claim 1 , wherein x=0.98. 10. The method according to claim 1 , wherein the semiconductor layer sequence is a thin film chip. 11. The method according to claim 1 , wherein the substrate is GaAs. 12. The method according to claim 1 , wherein the sacrificial layer completely oxidizes and an adhesion of the oxidized sacrificial layer is less than an adhesion of the non-oxidized sacrificial layer. 13. An optoelectronic component produced according to the method of claim 1 . 14. A method of producing a plurality of optoelectronic components, the method comprising: providing a substrate; epitaxially applying a sacrificial layer on the substrate, wherein the sacrificial layer has a layer thickness greater than 300 nm, and wherein the sacrificial layer comprises Al x Ga (1-x) As with 0<x≤1; epitaxially applying a semiconductor layer sequence on the sacrificial layer; forming trenches extending in a vertical direction through the semiconductor layer sequence to the sacrificial layer such that a plurality of regions in the semiconductor layer sequence is formed; and wet thermally oxidizing the sacrificial layer such that the substrate is non-destructively removable from the semiconductor layer sequence, wherein the sacrificial layer comprises at least three and optionally four sublayers in a direction facing away from the substrate, a first sublayer comprising InGaAlP, a second sublayer comprising GaAs, a third sublayer comprising Al x Ga (1-x) As with 0<x≤1 and a fourth sublayer comprising GaAs, and wherein the first sublayer is arranged on the substrate followed by the second sublayer, the third sublayer and the fourth sublayer in the direction facing away from the substrate. 15. The method according to claim 14 , further comprising: applying an auxiliary carrier to a side of the semiconductor layer sequence opposite the substrate after forming trenches and after wet thermally oxidizing; removing the auxiliary carrier and the semiconductor layer sequence from the substrate; and subsequently separating at least the auxiliary carrier so that the plurality of optoelectronic components is obtained. 16. The method according to claim 14 , wherein wet thermally oxidizing is carried out at a temperature of less than 400° C. under a steam atmosphere. 17. The method according to claim 14 , wherein 0.95≤x<1, and wherein the layer thickness of the sacrificial layer is between 600 nm and 800 nm, inclusive.

Assignees

Inventors

Classifications

  • of packages · CPC title

  • of coatings · CPC title

  • comprising only Group III-V materials, e.g. GaP · CPC title

  • Manufacture or treatment · CPC title

  • with a substrate not being Group III-V materials · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10950746B2 cover?
A method for producing a plurality of optoelectronic components are disclosed. In an embodiment, the method includes providing a substrate, epitaxially applying a sacrificial layer on the substrate, wherein the sacrificial layer has a layer thickness greater than 300 nm and comprises AlxGa(1-x)As with 0<x≤1, epitaxially applying a semiconductor layer sequence on the sacrificial layer, forming t…
Who is the assignee on this patent?
Osram Opto Semiconductors Gmbh, Osram Oled Gmbh
What technology area does this patent fall under?
Primary CPC classification H10H20/0133. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).