Ultra-low profile package shielding technique using magnetic and conductive layers for integrated switching voltage regulator

Patent metadata

Field	Value
Publication number	US-10950555-B2
Application number	US-201716481031-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a foundation layer;
a conductive layer formed on the foundation layer; and
a magnetic layer formed between the conductive layer and the foundation layer, wherein the conductive layer and the magnetic layer are coupled to form a low-profile inductor shield.

2. The semiconductor package of claim 1 , further comprising a dielectric layer formed between the magnetic layer and the foundation layer.

3. The semiconductor package of claim 1 , wherein the low-profile inductor shield includes one or more solder pads that are coupled to the conductive layer.

4. The semiconductor package of claim 1 , wherein the foundation layer further includes at least one of a voltage regulator and an inductor, and wherein the inductor is located above the low-profile inductor shield.

5. The semiconductor package of claim 1 , wherein the foundation layer further includes one or more vias and a ground via, and wherein the conductive layer is coupled to the one or more vias and the ground via.

6. The semiconductor package of claim 1 , further comprising a motherboard, a hole in motherboard of the motherboard, and a semiconductor die, wherein the semiconductor die is mounted to the foundation layer.

7. The semiconductor package of claim 6 , wherein the foundation layer is mounted between the motherboard and the semiconductor die, and wherein the foundation layer is attached to the motherboard with a plurality of solder balls.

8. The semiconductor package of claim 7 , wherein the low-profile inductor shield comprises a z-height that is less than a z-height of the plurality of solder balls.

9. The semiconductor package of claim 1 , wherein the low-profile inductor shield is formed on the foundation layer to suppress an electromagnetic interference and a radio frequency interference.

10. The semiconductor package of claim 1 , wherein the foundation layer is a printed circuit board.

11. A method of forming a semiconductor package, comprising:
mounting a foundation layer over a motherboard;
forming a conductive layer on the foundation layer; and
forming a magnetic layer between the conductive layer and the foundation layer, wherein the conductive layer and the magnetic layer are coupled to form a low-profile inductor shield.

12. The method of claim 11 , further comprising forming a dielectric layer between the magnetic layer and the foundation layer.

13. The method of claim 11 , wherein the low-profile inductor shield includes one or more solder pads that are coupled to the conductive layer.

14. The method of claim 11 , wherein the foundation layer further includes at least one of a voltage regulator and an inductor, and wherein the inductor is located above the low-profile inductor shield.

15. The method of claim 11 , wherein the foundation layer further includes one or more vias and a ground via, and wherein the conductive layer is coupled to the one or more vias and the ground via.

16. The method of claim 11 , further comprising mounting a semiconductor die to the foundation layer.

17. The method of claim 16 , wherein the foundation layer is mounted between the motherboard and the semiconductor die, and wherein the foundation layer is attached to the motherboard with a plurality of solder balls.

18. The method of claim 17 , wherein the low-profile inductor shield comprises a z-height that is less than a z-height of the plurality of solder balls.

19. The method of claim 11 , wherein the low-profile inductor shield is formed on the foundation layer to suppress an electromagnetic interference and a radio frequency interference.

20. The method of claim 11 , wherein the foundation layer is a printed circuit board.

21. A semiconductor package, comprising:
a foundation layer;
a conductive layer formed on the foundation layer;
a magnetic layer formed between the conductive layer and the foundation layer; and
a magnetic inductor array (MIA) embedded within the magnetic layer, wherein the conductive layer, the magnetic layer, and the magnetic inductor array are coupled to form a low-profile inductor shield.

22. The semiconductor package of claim 21 , wherein the low-profile inductor shield includes one or more MIA pads and one or more solder pads, wherein the one or more solder pads are coupled to the conductive layer, wherein the one or more MIA pads are coupled to the MIA, and wherein the low-profile inductor shield is mounted below the foundation layer.

23. The semiconductor package of claim 21 , wherein the foundation layer further includes at least one of a voltage regulator and an inductor.

24. The semiconductor package of claim 21 , wherein the foundation layer further includes one or more vias and a ground via, and wherein the conductive layer is coupled to the one or more vias and the ground via.

25. The semiconductor package of claim 21 , further comprising a motherboard, a hole in motherboard of the motherboard, a semiconductor die, wherein the semiconductor die is mounted to the foundation layer, wherein the foundation layer is mounted between the motherboard and the semiconductor die, wherein the foundation layer is attached to the motherboard with a plurality of solder balls, and wherein the low-profile inductor shield comprises a z-height that is less than a z-height of the plurality of solder balls.

Assignees

• Intel Corp

Inventors

• Radhakrishnan Kaladhar
• Lee Jaejin
• Hsu Hao-Han
• Chen Chung-Hao J
• Han Dong-Ho

Classifications

• H10W44/243

  for decoupling, e.g. bypass capacitors · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title