Resin encapsulated power semiconductor module with exposed terminal areas

Patent metadata

Field	Value
Publication number	US-10950516-B2
Application number	US-201916673201-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	May 2, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A power semiconductor module includes a substrate with a metallization layer; at least one power semiconductor chip bonded to the substrate; and a mold encapsulation partially encapsulating the semiconductor chip and the substrate; the mold encapsulation includes at least one window exposing a terminal area of the metallization layer; and a border part of the mold encapsulation between the window and a border of the substrate has a height over the substrate smaller than a maximal height of a central part of the mold encapsulation.

First claim

The invention claimed is:

1. A power semiconductor module, comprising:
a substrate with a metallization layer;
at least one power semiconductor chip bonded to the substrate;
a mold encapsulation partially encapsulating the semiconductor chip and the substrate, wherein the mold encapsulation comprises at least one window exposing a terminal area of the metallization layer;
a power terminal bonded with an end to the terminal area;
wherein the mold encapsulation comprises a central part, which encapsulates the semiconductor chip;
wherein a border part of the mold encapsulation between the window and a border of the substrate has a height over the substrate smaller than a maximal height over the substrate of the central part of the mold encapsulation;
wherein a part of the power terminal protrudes above the border part in a direction parallel to the substrate, such that a vertical height over the substrate of the part is smaller than the maximal height of the central part of the mold encapsulation.

2. The power semiconductor module of claim 1 ,
wherein the height over the substrate of the border part is smaller than a maximal height of conductors over the substrate, wherein the conductors are encapsulated in the mold encapsulation and are bonded to the semiconductor chip and the metallization layer.

3. The power semiconductor module of claim 2 , wherein the border part overlaps the border of the substrate.

4. The power semiconductor module of claim 3 , wherein the mold encapsulation comprises at least two windows, each window exposing a terminal area of the metallization layer;
wherein at least one of the terminal areas is a power terminal area;
wherein at least one of the terminal areas is an auxiliary terminal area.

5. The power semiconductor module of claim 2 , wherein the mold encapsulation comprises at least two windows, each window exposing a terminal area of the metallization layer;
wherein at least one of the terminal areas is a power terminal area;
wherein at least one of the terminal areas is an auxiliary terminal area.

6. The power semiconductor module of claim 2 , further comprising:
two power terminals with two coplanar conductor strips;
wherein each power terminal comprises at least two feet protruding from the respective conductor strip, such that a foot from the one power terminal alternates with a foot from the other one power terminal;
wherein the feet from the power terminals are bonded to a row of terminal areas, each of which is provided by a dedicated window in the mold encapsulation.

7. The power semiconductor module of claim 1 , wherein the border part overlaps the border of the substrate.

8. The power semiconductor module of claim 7 , wherein the mold encapsulation comprises at least two windows, each window exposing a terminal area of the metallization layer;
wherein at least one of the terminal areas is a power terminal area;
wherein at least one of the terminal areas is an auxiliary terminal area.

9. The power semiconductor module of claim 7 , wherein the border part provides at least two windows.

10. The power semiconductor module of claim 1 , wherein the mold encapsulation comprises at least two windows, each window exposing a terminal area of the metallization layer;
wherein at least one of the terminal areas is a power terminal area;
wherein at least one of the terminal areas is an auxiliary terminal area.

11. The power semiconductor module of claim 1 , wherein the border part provides at least two windows.

12. The power semiconductor module of claim 1 , further comprising:
two power terminals with two coplanar conductor strips;
wherein each power terminal comprises at least two feet protruding from the respective conductor strip, such that a foot from the one power terminal alternates with a foot from the other one power terminal;
wherein the feet from the power terminals are bonded to a row of terminal areas, each of which is provided by a dedicated window in the mold encapsulation.

13. The power semiconductor module of claim 1 , further comprising:
an auxiliary terminal bonded with a first end to a terminal area in a window in the mold encapsulation and with a second end protruding above the central part.

14. The power semiconductor module of claim 1 , further comprising:
a circuit board attached to the central part of the mold encapsulation;
at least one of a bond wire bonded to a terminal area in a window and bonded to the circuit board and an electrically conducting spring element connected to the printed circuit board and pressed against a terminal area in a window.

15. The power semiconductor module of claim 1 , wherein an end of a terminal bonded to a terminal area in a window in the mold encapsulation is embedded in a casting material filled into the window.

16. The power semiconductor module of claim 1 , further comprising:
a cooling plate attached to the substrate opposite to the power semiconductor chip;
wherein the mold encapsulation is provided solely on one side of the cooling plate;
wherein the border part of the mold encapsulation extends over the border of the substrate and is deposited on the cooling plate.

17. The power semiconductor module of claim 16 , further comprising:
a cooling body with a cooling cavity, which is closed by the cooling plate inserted into the cooling body;
wherein the cooling plate is welded to the cooling body along a border of the cooling plate.

18. A power semiconductor module assembly, comprising:
a power semiconductor module according to claim 1 ;
a power electrical device;
wherein the power terminal directly interconnects the power electrical device with the power semiconductor module.

19. A method of manufacturing a power semiconductor module, the method comprising:
providing a substrate with a metallization layer, with at least one power semiconductor chip bonded to the substrate;
molding the semiconductor chip and the substrate into a mold encapsulation, wherein the mold encapsulation comprises a central part, which encapsulates the semiconductor chip, and the mold encapsulation comprises at least one window exposing a terminal area of the metallization layer and wherein a border part of the encapsulation between the window and a border of the substrate has a height over the substrate smaller than a maximal height of the central part of the mold encapsulation;
bonding a power terminal with an end to the terminal area;
wherein a part of the power terminal protrudes above the border part in a direction parallel to the substrate, such that a vertical height over the substrate of the part is smaller than the maximal height of the central part of the mold encapsulation.

20. The method of claim 19 , further comprising:
welding a cooling plate attached to the substrate to a cooling body;
bonding an auxiliary terminal to a terminal area provided in a window of the mold encapsulation;
bonding a conductor strip to a terminal area provided in a window and to a power electrical device.

Assignees

• Abb Schweiz Ag
• Audi Ag

Inventors

• Mohn Fabian

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/016

  using moulds · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title