Event counters for memory operations

Patent metadata

Field	Value
Publication number	US-10950308-B2
Application number	US-202016927473-A
Country	US
Kind code	B2
Filing date	Jul 13, 2020
Priority date	Oct 24, 2018
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

First claim

What is claimed is:

1. A memory system, comprising:
an array of memory cells; and
a counter coupled to the array and configured to determine whether a threshold quantity of memory cells of a group of memory cell in the array experience a switching event in response to a read voltage applied across the group of memory cells;
wherein the counter comprises:
a plurality of sensing components, each respective sensing component configured to sense a respective event and comprising a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event and
a comparator comprising a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events, the comparator configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

2. A system, comprising:
a memory comprising an array of memory cells; and
a counter coupled to the memory and comprising a number of sensing components and a compartor;
wherein each respective sensing component comprises a first capacitor initially charged to a first voltage and is configured to receive a respective second voltage indicative of a respective event;
wherein each respective first capacitor is configured to be coupled in parallel with a second capacitor of the counter in response to each respective sensing component receiving the respective first voltage so that each respective first capacitor discharges into the second capacitor until each respective first capacitor and the second capacitor reach a third voltage; and
wherein the comparator is configured to compare the third voltage to a reference voltage to determine whether the number of sensing components receiving the respective second voltage is greater than or equal to a threshold quantity.

3. The system of claim 2 , wherein the comparator is configured to output a signal in response to the third voltage being greater than or equal to the reference voltage to indicate that the number of sensing components receiving the respective second voltage is greater than or equal to the threshold quantity.

4. The system of claim 2 , wherein the second capacitor is one of a plurality of second capacitors that are coupled in parallel to an input of the comparator and that are coupled in parallel with each respective first capacitor in response to each respective sensing component receiving the respective second voltage so that each respective first capacitor discharges into the plurality of second capacitors until each respective first capacitor and the plurality of second capacitors reach the third voltage.

5. The memory system of claim 1 , wherein the read voltage is an increasing ramp voltage.

6. The memory system of claim 1 , wherein the switching event corresponds to a state transition of the respective memory cells.

7. The memory system of claim 1 , wherein the array of memory cells comprises resistance variable memory cells.

8. The memory system of claim 1 , wherein the counter is configured to detect concurrent switching events.

9. The memory system of claim 1 , wherein the array of memory cells comprises a three dimensional (3D) cross point array with the group of cells being commonly coupled to an access line and to respective data lines.

10. The memory system of claim 9 , further comprising sense amplifiers coupled to the respective data lines.

11. The memory system of claim 1 , wherein the memory system comprises a controller configured to receive commands from a host.

12. The memory system of claim 1 , wherein the threshold quantity of memory cells corresponds to a weight of a data pattern stored in the group of memory cells.

13. The memory system of claim 1 , wherein the second capacitor is configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor.

14. A computing system, comprising:
a host;
a memory system coupled to the host and comprising:
a system controller; and
a memory coupled to the system controller and comprising:
an embedded controller;
a memory array coupled to the embedded controller; and
a counter comprising a number of sensing components, the counter configured to:
receive a respective first voltage indicative of a respective switching event at each respective sensing component of the number of sensing components, each respective sensing component comprising a respective first capacitor initially charged to a second voltage;
transfer a particular amount of charge from each respective first capacitor into an initially discharged second capacitor by discharging each respective first capacitor into the second capacitor in response to each respective sensing component receiving the respective first voltage so that the second capacitor is charged to a third voltage; and
compare the third voltage to a reference voltage by a comparator to determine whether the number of sensing components receiving the respective first voltage is greater than or equal to a threshold quantity.

15. The computing system of claim 14 , wherein the third voltage is directly proportional to the number of sensing components receiving the respective first voltage.

16. The computing system of claim 14 , wherein the threshold quantity corresponds to a weight of a data pattern stored in a group of memory cells of the memory array.

17. The computing system of claim 14 , wherein the counter is configured to determine the quantity of cells of a group of cells of the memory array that experience the switching event responsive to a read voltage applied across the group.

18. The computing system of claim 17 , wherein the read voltage is an increasing ramp voltage.

19. The computing system of claim 14 , wherein the memory array is a 3D XPoint array.

20. The computing system of claim 14 , wherein the number of sensing components comprise respective sense amplifiers.

Assignees

• Micron Technology Inc

Inventors

• Sforzin Marco
• Di Vincenzo Umberto

Classifications

• H03K25/02

  comprising charge storage, e.g. capacitor without polarisation hysteresis · CPC title

• H03K23/44

  using field-effect transistors {(H03K23/46 and H03K23/425 take precedence)} · CPC title

• H03K21/38 Primary

  Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title

• G11C16/12 Primary

  Programming voltage switching circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title