Array data bit inversion

Patent metadata

Field	Value
Publication number	US-10043566-B2
Application number	US-201715641020-A
Country	US
Kind code	B2
Filing date	Jul 3, 2017
Priority date	Jun 21, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

First claim

What is claimed is:

1. A method, comprising:
applying a first voltage across a memory cell;
deactivating a first transistor that is in electronic communication with a first input of a sense component and the memory cell based at least in part on applying the first voltage;
activating the sense component based at least in part on deactivating the first transistor;
activating a second transistor that is in electronic communication with a second input of the sense component and the memory cell based at least in part on activating the sense component; and
applying a second voltage across the memory cell based at least in part on activating the second transistor.

2. The method of claim 1 , further comprising:
applying a third voltage across a reference cell; and
deactivating a third transistor that is in electronic communication with the second input of the sense component and the reference cell based at least in part on applying the first voltage across the memory cell and applying the third voltage across the reference cell.

3. The method of claim 2 , further comprising:
activating a fourth transistor that is in electronic communication with the first input of the sense component and the reference cell based at least in part on activating the sense component.

4. The method of claim 1 , wherein applying the second voltage across the memory cell comprises:
applying a third voltage to a bit line that is in electronic communication with the memory cell via the second transistor, the third voltage comprising a voltage at the second input of the sense component based at least in part on activating the sense component; and
applying a fourth voltage to a plate line that is in electronic communication with the memory cell during an overlapping time period with applying the third voltage.

5. The method of claim 1 , wherein applying the first voltage across the memory cell comprises:
applying a third voltage to a selection component that is in electronic communication with a storage component of the memory cell and a bit line that is in electronic communication with the memory cell and the first transistor; and
applying a fourth voltage to a plate line that is in electronic communication with the memory cell.

6. The method of claim 1 , wherein the memory cell stores a first logic state before the first voltage is applied and stores a second logic state, different than the first logic state, after the second voltage is applied.

7. The method of claim 6 , further comprising:
applying a third voltage across the memory cell after applying the second voltage;
deactivating the first transistor that is in electronic communication with the first input of the sense component and the memory cell based at least in part on applying the first voltage across the memory cell;
activating the sense component based at least in part on deactivating the first transistor;
activating the second transistor that is in electronic communication with the second input of the sense component and the memory cell based at least in part on activating the sense component; and
applying a fourth voltage across the memory cell based at least in part on activating the second transistor, wherein the memory cell stores the first logic state after the fourth voltage is applied.

8. The method of claim 6 , further comprising:
performing a read operation of the memory cell after applying the second voltage, wherein reading the memory cell comprises deactivating the first transistor and activating the second transistor for the read operation based at least in part on the memory cell storing the second logic state.

9. The method of claim 1 , further comprising:
updating a value of a counter based at least in part on activating the second transistor, wherein the value of the counter is associated with an address used for accessing the memory cell.

10. The method of claim 9 , further comprising:
comparing the value of the counter with the address used for accessing the memory cell; and
performing a read operation of the memory cell after applying the second voltage, wherein reading the memory cell comprises deactivating the first transistor and activating the second transistor for the read operation based at least in part on the comparison of the value of the counter with the address.

11. An apparatus, comprising:
a bit line;
a reference bit line;
a sense component comprising a first input line and a second input line;
a first transistor in electronic communication with and between the bit line and the first input line of the sense component;
a second transistor in electronic communication with and between the bit line and the second input line of the sense component;
a third transistor in electronic communication with and between the reference bit line and the first input line of the sense component; and
a fourth transistor in electronic communication with and between the reference bit line and the second input line of the sense component.

12. The apparatus of claim 11 , further comprising:
a ferroelectric memory cell in electronic communication with the bit line.

13. The apparatus of claim 11 , wherein:
the first transistor, the second transistor, and the bit line share a first common node, the first transistor being physically or electrically between the first common node and the first input line of the sense component and the second transistor being physically or electrically between the first common node and the second input line of the sense component; and
the third transistor, the fourth transistor, and the reference bit line share a second common node, the third transistor being physically or electrically between the second common node and the first input line of the sense component and the fourth transistor being physically or electrically between the second common node and the second input line of the sense component.

14. An apparatus, comprising:
an access line;
a reference line;
a sense component comprising a first input line and a second input line;
a first transistor in electronic communication with the access line and the first input line of the sense component;
a second transistor in electronic communication with the access line and the second input line of the sense component;
a third transistor in electronic communication with the reference line and the first input line of the sense component;
a fourth transistor in electronic communication with the reference line and the second input line of the sense component;
a first set of control lines in electronic communication with the first transistor and the second transistor;
a second set of control lines in electronic communication with the third transistor and the second transistor; and
a counter in electronic communication with the first set of control lines and the second set of control lines.

15. The apparatus of claim 14 , wherein the counter comprises a non-volatile latch.

16. The apparatus of claim 11 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are external to the sense component.

17. An apparatus, comprising:
a memory cell;
a sense component;
a first transistor in electronic communication a first input of the sense component and the memory cell;
a second transistor in electronic communication with a second input of the sense component and the memory cell; and
a controller in electronic communication with the memory cell, the first transistor, the second transistor, and the sense component, wherein the controller comprises code executabl

Assignees

• Micron Technology Inc

Inventors

• Ingalls Charles L
• Derner Scott J

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title