Layout design system and layout design method

Patent metadata

Field	Value
Publication number	US-10949595-B2
Application number	US-201816622054-A
Country	US
Kind code	B2
Filing date	Jun 14, 2018
Priority date	Jun 22, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A system performs a layout design of a circuit for a small area satisfying a design rule within a short period of time. In a layout design system which includes a processing portion and in which a circuit diagram and layout design information are input to the processing portion, the processing portion has a function of generating layout data from the circuit diagram and the layout design information by performing a Q learning, the processing portion has a function of outputting the layout data, the processing portion includes a first neural network, and the first neural network estimates an action value function in the Q learning.

First claim

The invention claimed is:

1. A layout design system comprising a processing portion,
wherein a circuit diagram and layout design information are input to the processing portion,
wherein the processing portion has a function of generating layout data from the circuit diagram and the layout design information by performing a Q learning,
wherein the processing portion has a function of outputting the layout data,
wherein the processing portion comprises a first neural network, and
wherein the first neural network estimates an action value function in the Q learning.

2. The layout design system according to claim 1 , wherein the first neural network is a convolutional neural network.

3. The layout design system according to claim 1 ,
wherein the processing portion further comprises a second neural network,
wherein the second neural network estimates teacher data for the action value function, and
wherein a weight coefficient of the first neural network is updated in accordance with a loss function calculated from the teacher data.

4. The layout design system according to claim 3 , wherein the second neural network is a convolutional neural network.

5. The layout design system according to claim 1 ,
wherein the processing portion comprises a transistor, and
wherein the transistor comprises a metal oxide in a channel formation region.

6. The layout design system according to claim 1 ,
wherein the processing portion comprises a transistor, and
wherein the transistor comprises silicon in a channel formation region.

7. A layout design system comprising a terminal and a server,
wherein the terminal comprises an input/output portion and a first communication portion,
wherein the server comprises a processing portion and a second communication portion,
wherein a circuit diagram and layout design information are input to the input/output portion,
wherein the first communication portion has a function of supplying the circuit diagram and the layout design information to the server by one or both of a wire communication and a wireless communication,
wherein the processing portion has a function of generating layout data from the circuit diagram and the layout design information by performing a Q learning,
wherein the processing portion has a function of supplying the layout data to the second communication portion,
wherein the second communication portion has a function of supplying the layout data to the terminal by one or both of a wire communication and a wireless communication,
wherein the processing portion comprises a first neural network, and
wherein the first neural network estimates an action value function in the Q learning.

8. The layout design system according to claim 7 , wherein the first neural network is a convolutional neural network.

9. The layout design system according to claim 7 ,
wherein the processing portion further comprises a second neural network,
wherein the second neural network estimates teacher data for the action value function, and
wherein a weight coefficient of the first neural network is updated in accordance with a loss function calculated from the teacher data.

10. The layout design system according to claim 9 , wherein the second neural network is a convolutional neural network.

11. The layout design system according to claim 7 ,
wherein the processing portion comprises a transistor, and
wherein the transistor comprises a metal oxide in a channel formation region.

12. The layout design system according to claim 7 ,
wherein the processing portion comprises a transistor, and
wherein the transistor comprises silicon in a channel formation region.

13. A layout design method comprising:
inputting a circuit diagram and layout design information;
performing a Q learning from the circuit diagram and the layout design information to generate layout data;
estimating an action value function using a first neural network in the Q learning; and
outputting the layout data.

14. The layout design method according to claim 13 , further comprising:
estimating teacher data for the action value function using a second neural network, and
updating a weight coefficient of the first neural network in accordance with a loss function calculated from the teacher data.

Assignees

• Semiconductor Energy Lab

Inventors

• Tsutsui Naoaki
• Koumura Yusuke
• Iwaki Yuji
• Yamazaki Shunpei

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/092

  Reinforcement learning · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title