Data processor using a ring bus and method for controlling the same

Patent metadata

Field	Value
Publication number	US-10949369-B2
Application number	US-202016846979-A
Country	US
Kind code	B2
Filing date	Apr 13, 2020
Priority date	Dec 21, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

First claim

What is claimed is:

1. A data processor comprising:
a plurality of relay circuits;
a plurality of bus masters, each of the bus masters which is coupled to an associated one of the relay circuits;
a plurality of slaves to which the bus masters access; and
a ring bus through which the relay circuits are coupled in the shape of a ring,
wherein each of the relay circuits includes:
an arbitration circuit which receives an adjacent request packet from an adjacent relay circuit and a bus request packet from the associated one of the bus masters, and arbitrates the adjacent request packet and the bus request packet based on priority of the adjacent request packet and priority of the bus request packet, and outputs one of the adjacent request packet and the bus request packet to a next relay circuit based on an arbitration result,
a priority adjustment circuit which has a table in which the predetermined threshold value set based on the number of the relay circuits through which the bus request packet passes before reaching its destination is stored, and adjusts the priority of the bus request packet based on the predetermined threshold value corresponding the destination of the bus request packet according to the arbitration result.

2. The data processor according to claim 1 ,
wherein the priority adjustment circuit adjusts the priority of the bus request packet when the number of times the bus request packet is rejected in the arbitration circuit exceeds the predetermined threshold value corresponding the destination of the bus request packet.

3. The data processor according to claim 1 ,
wherein the predetermined threshold value is set such that the greater the number of the relay circuits through which the bus request packet passes before reaching its destination is, the smaller the predetermined threshold value is.

4. The data processor according to claim 1 ,
wherein the priority adjustment circuit further includes:
a counter which counts the number of times the bus request packet is rejected in the arbitration circuit,
a comparison circuit which compares the number of times the bus request packet is rejected in the arbitration circuit with the predetermined threshold value corresponding the destination of the bus request packet; and
an adding circuit which adds a predetermined value to the priority of the bus request packet when the number of times the bus request packet is rejected exceeds the predetermined threshold value corresponding the destination of the bus request packet.

5. The data processor according to claim 1 , further comprising a monitor circuit monitors the amount of request packets in the ring bus,
wherein the monitor circuit limits transferring the request packet of the bus master to the relay circuit.

6. The data processor according to claim 1 ,
wherein each of the relay circuits includes a buffer circuit which temporarily holds request packets outputted from the arbitration circuit, and
wherein the buffer circuit changes the order of holding request packets to output to the next relay circuit according to the priority of the holding request packets.

7. The data processor according to claim 1 ,
wherein the ring bus includes a first ring bus and a second ring bus,
wherein the relay circuits include first relay circuits and second relay circuits,
wherein the first relay circuits are coupled through the first ring bus and transfer request packets in a first direction, and
wherein the second relay circuits are coupled through the second ring bus and transfer request packets in a second direction being opposite to the first direction.

8. The data processor according to claim 2 ,
wherein the priority adjustment circuit adjusts such that the priority of the bus request packet become higher when the number of times the bus request packet is rejected in the arbitration circuit exceeds the predetermine threshold value corresponding the destination of the bus request packet.

9. The data processor according to claim 5 ,
wherein each of the relay circuits includes a buffer circuit which temporarily holds request packets from the arbitration circuit, and
wherein the monitor circuit monitors the amount of request packets in the ring bus by monitoring of request packets held in the buffer circuit.

10. The data processor according to claim 6 ,
wherein the buffer circuit includes:
a first holding circuit holding a first request packet;
a second holding circuit coupled to the first holding circuit and holding a second request packet inputted after input of the first request packet; and
a selection circuit selecting one of the first and the second request packet according to priorities of the first and the second request packet to output to the next relay circuit.

11. A data processor, comprising:
a plurality of relay circuits;
a plurality of bus masters;
a plurality of slaves which are accessed from the bus masters, each of the slaves which is coupled to an associated one of relay circuits; and
a ring bus through which the relay circuits are coupled in the shape of a ring;
wherein each of the relay circuits includes:
an arbitration circuit which receives an adjacent response packet from an adjacent relay circuit and a slave response packet from the associated one of the slaves, and arbitrates the adjacent response packet and the slave response packet based on priority of the adjacent response packet and priority of the slave response packet to output one of the adjacent response packet and the slave response packet to a next relay circuit based on an arbitration result,
a priority adjustment circuit which has a table in which the predetermined threshold value based on the number of the relay circuits through which the slave response packet passes before reaching its destination is stored, and adjusts the priority of the slave response packet based on the predetermined threshold value corresponding the destination of the slave response packet according to arbitration result.

Assignees

• Renesas Electronics Corp

Inventors

• Koike Manabu

Classifications

• G06F13/4004 Primary

  Coupling between buses · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title

• G06F13/4247

  on a daisy chain bus · CPC title

• G06F13/374

  using a self-select method with individual priority code comparator · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title