Data processor using a ring bus and method for controlling the same

Patent metadata

Field	Value
Publication number	US-10628360-B2
Application number	US-201816178302-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Dec 21, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

First claim

What is claimed is:

1. A data processor, comprising:
a plurality of bus masters;
a plurality of slaves to which the bus masters can make access;
a plurality of relay circuits each of which is coupled to each of the bus masters and each of the slaves; and
a ring bus through which the relay circuits are coupled in the shape of a ring,
wherein the relay circuit includes:
an arbitration circuit which arbitrates an adjacent request packet being a request packet of an adjacent relay circuit and a bus request packet being a request packet of a nearest bus master with use of priority of the adjacent request packet and priority of the bus request packet when the adjacent request packet and the bus request packet conflict each other, and outputs the request packet after arbitration to a next relay circuit; and
a priority adjustment circuit which adjusts the priority of the bus request packet according to the number of the relay circuits through which the bus request packet passes before reaching its destination.

2. The data processor according to claim 1 ,
wherein the priority adjustment circuit is so configured as to adjust such that the priority of the bus request packet becomes higher when the number of times the bus request packet is rejected in the arbitration circuit exceeds a predetermine threshold value, and
wherein the predetermined threshold value is set such that the greater the number of the relay circuits through which the bus request packet passes before reaching its destination is, the smaller the predetermined threshold value is.

3. The data processor according to claim 1 further comprising a monitor circuit which monitors the amount of request packets in the ring bus,
wherein the monitor circuit limits request packets to be sent to the relay circuit from the bus master according to the amount of request packets in the ring bus.

4. The data processor according to claim 1 ,
wherein the relay circuit includes a buffer circuit which temporarily holds the request packets outputted from the arbitration circuit, and
wherein the buffer circuit is so configured as to be able to change the order of the request packets to be outputted to a next destination according to the priority of the request packets.

5. The data processor according to claim 1 ,
wherein the ring bus includes:
a first ring bus which transfers request packets in a first direction; and
a second ring bus which transfers request packets in a second direction being opposite to the first direction, and

wherein the relay circuit is provided in each of the first and second ring buses.

6. The data processor according to claim 1 further comprising:
a relay circuit for response being coupled to each of the bus masters and each of the slaves; and
a ring bus for response through which the relay circuits for response are coupled in the shape of a ring,
wherein the relay circuit for response includes:
an arbitration circuit for response which arbitrates an adjacent response packet being a response packet of an adjacent relay circuit and a slave response packet being a response packet of a nearest slave with use of priority of the adjacent response packet and priority of the slave response packet, and outputs the response packet after arbitration to a next relay circuit; and
a priority adjustment circuit for response which adjusts the priority of the slave response packet according to the number of relay circuits for response through which the slave response packet passes before reaching its destination.

7. The data processor according to claim 1 ,
wherein the priority adjustment circuit is configured to adjust the priority of the bus request packet when the bus request packet is rejected for predetermined number of times by the arbitration circuit.

8. The data processor according to claim 2 ,
wherein the priority adjustment circuit includes:
a table in which the predetermined threshold value is stored;
a counter which counts the number of times the bus request packet is rejected in the arbitration circuit;
a comparison circuit which compares the number of times the bus request packet is rejected in the arbitration circuit with the predetermined threshold value; and
an adding circuit which adds a predetermined value to priority of the bus request packet when the number of times the bus request packet is rejected exceeds the predetermined threshold value.

9. The data processor according to claim 3 ,
wherein the relay circuit includes a buffer circuit which temporarily holds request packets outputted from the arbitration circuit, and
wherein the monitor circuit monitors the amount of request packets in the ring bus by monitoring the amount of request packets held in the buffer circuit.

10. The data processor according to claim 4 ,
wherein the buffer circuit includes:
a first holding circuit capable of holding a first request packet;
a second holding circuit which is provided immediately after the first holding circuit and is capable of holding a second request packet; and
a selection circuit which selects one of the first request packet held in the first holding circuit and the second request packet held in the second holding circuit, and

wherein the selection circuit selects and outputs the request packet having higher priority out of the first and second request packets.

11. The data processor according to claim 8 , wherein, after adding the predetermined value to the priority of the bus request packet, the adding circuit further adds a predetermined value to the priority of the bus request packet again when the bus request packet is rejected in the arbitration circuit.

12. The data processor according to claim 9 ,
wherein the monitor circuit limits request packets to be supplied to each of the relay circuits from each of the bus masters when there is no vacancy in at least one of the buffer circuits included in the respective relay circuits.

13. A data processor, comprising:
a plurality of bus masters;
a plurality of slaves to which the bus masters can make access;
a plurality of relay circuits each of which is coupled to each of the bus masters and each of the slaves; and
a ring bus through which the relay circuits are coupled in the shape of a ring,
wherein the relay circuit includes:
an arbitration circuit which arbitrates an adjacent response packet being a response packet of an adjacent relay circuit and a slave response packet being a response packet of a nearest slave with use of priority of the adjacent response packet and priority of the slave response packet when the adjacent response packet and the slave response packet conflict each other, and outputs the response packet after arbitration to a next relay circuit; and
a priority adjustment circuit which adjusts the priority of the slave response packet according to the number of the relay circuits through which the slave response packet passes before reaching its destination.

14. A method for controlling a data processor, the data processor comprising:
a plurality of bus masters;
a plurality of slaves to which the bus masters make access;
a plurality of relay circuits each of which is coupled to each of the bus masters and each of the slaves; and
a ring bus through which the relay circuits are coupled in the shape of a ring,
wherein, when arbitrating an adjacent request packet being a request packet of an adjacent relay circuit and a bus request packet being a request packet of a nearest bus master with use of priority of the adjacent request packet and priority of the bus request packet when the adjacent request packet and the bus request packet

Assignees

• Renesas Electronics Corp

Inventors

• Koike Manabu

Classifications

• G06F13/4247

  on a daisy chain bus · CPC title

• G06F13/372 Primary

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title

• G06F13/374

  using a self-select method with individual priority code comparator · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title