Offset correction for pseudo differential signaling

Patent metadata

Field	Value
Publication number	US-10944368-B2
Application number	US-201916289247-A
Country	US
Kind code	B2
Filing date	Feb 28, 2019
Priority date	Feb 28, 2019
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.

First claim

What is claimed is:

1. A system comprising:
an offset correction circuit; and
a receiver component, wherein the receiver component receives an input signal on a positive input terminal;
wherein the offset correction circuit is configured to:
apply a positive offset voltage to a termination voltage that is coupled to a midpoint between a pair of resistors;
apply a negative offset voltage to the termination voltage; and
connect either the positive offset voltage applied to the termination voltage or the negative offset voltage applied to the termination voltage to a negative input terminal of the receiver component;

wherein the receiver component is configured to generate an output voltage based on a comparison between the positive input terminal and the negative input terminal.

2. The system as recited in claim 1 , wherein the positive offset voltage applied to the termination voltage is generated on a top side of a first resistor of the pair of resistors.

3. The system as recited in claim 2 , wherein the negative offset voltage applied to the termination voltage is generated on a bottom side of a second resistor of the pair of resistors.

4. The system as recited in claim 3 , wherein the offset correction circuit is configured to drive a current through the pair of resistors.

5. The system as recited in claim 4 , wherein the offset correction circuit comprises a digital to analog converter (DAC) configured to adjust a magnitude of the current driven through the pair of resistors based on a calibration sequence.

6. The system as recited in claim 1 , wherein:
the positive offset voltage applied to the termination voltage is coupled to a first input of a multiplexer;
the negative offset voltage applied to the termination voltage is coupled to a second input of the multiplexer;
an output of the multiplexer is coupled to the negative input terminal of the receiver component; and
the receiver component is a sense amplifier.

7. A method comprising:
receiving an input signal on a positive input terminal of a receiver component;
applying a positive offset voltage to a termination voltage that is coupled to a midpoint between a pair of resistors;
applying a negative offset voltage to the termination voltage;
connecting either the positive offset voltage applied to the termination voltage or the negative offset voltage applied to the termination voltage to a negative input terminal of the receiver component; and
generating, by the receiver component, an output voltage based on a comparison between to the positive input terminal and the negative input terminal.

8. The method as recited in claim 7 , wherein the positive offset voltage applied to the termination voltage is generated on a top side of a first resistor of the pair of resistors.

9. The method as recited in claim 8 , wherein the negative offset voltage applied to the termination voltage is generated on a bottom side of a second resistor of the pair of resistors.

10. The method as recited in claim 9 , further comprising driving a current through the pair of resistors.

11. The method as recited in claim 10 , further comprising a digital to analog converter (DAC) adjusting a magnitude of the current driven through the pair of resistors based on a calibration sequence.

12. The method as recited in claim 7 , further comprising:
coupling the positive offset voltage applied to the termination voltage to a first input of a multiplexer;
coupling the negative offset voltage applied to the termination voltage is coupled to a second input of the multiplexer; and
coupling an output of the multiplexer to the negative input terminal of the receiver component, wherein the receiver component is a sense amplifier.

13. A circuit comprising:
a digital to analog converter (DAC); and
a receiver component which receives an input signal on a positive input terminal;
wherein the DAC is configured to:
apply a positive offset voltage to a termination voltage that is coupled to a midpoint between a pair of resistors;
apply a negative offset voltage to the termination voltage; and
connect either the positive offset voltage applied to the termination voltage or the negative offset voltage applied to the termination voltage to a negative input terminal of the receiver component;

wherein the receiver component is configured to generate an output voltage based on a comparison between the positive input terminal and the negative input terminal.

14. The circuit as recited in claim 13 , wherein the positive offset voltage applied to the termination voltage is generated on a top side of a first resistor of the pair of resistors.

15. The circuit as recited in claim 14 , wherein the negative offset voltage applied to the termination voltage is generated on a bottom side of a second resistor of the pair of resistors.

16. The circuit as recited in claim 15 , wherein the DAC is configured to drive a current through the pair of resistors.

17. The circuit as recited in claim 16 , wherein the DAC is configured to adjust a magnitude of the current driven through the pair of resistors based on a calibration sequence.

Assignees

• Advanced Micro Devices Inc

Inventors

• Paraschou Milam
• Cooper Jeffrey

Classifications

• H03F3/45991 Primary

  by using balancing means · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/45968 Primary

  by offset reduction · CPC title