Integrated silicon controlled rectifier (SCR) and a low leakage SCR supply clamp for electrostatic discharge (ESP) protection

Patent metadata

Field	Value
Publication number	US-10944257-B2
Application number	US-201815952466-A
Country	US
Kind code	B2
Filing date	Apr 13, 2018
Priority date	Apr 13, 2018
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.

First claim

The invention claimed is:

1. An electrostatic discharge (ESD) protection circuit, comprising:
a first power supply line;
a second power supply line;
a functional circuit electrically coupled for power supply to the first and second power supply lines;
an input/output pad coupled to the functional circuit;
a first protection diode connected between the input/output pad and the first power supply line;
a second protection diode connected between the input/output pad and the second power supply line;
a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, at least one trigger signal; and
a silicon controlled rectifier (SCR) having an anode terminal connected to the first power supply line and a cathode terminal connected to the second power supply line;
wherein the SCR further includes an embedded field effect transistor (FET) having an insulated gate which forms a control gate terminal coupled to receive said at least one trigger signal.

2. The ESD protection circuit of claim 1 , wherein a conduction terminal of the embedded FET forms the cathode terminal of the SCR.

3. The circuit of claim 1 , wherein the trigger circuit comprises:
a resistive-capacitive ESD detection circuit configured to generate an ESD detection signal;
a first inverter circuit having an input coupled to receive the ESD detection signal and an output configured to generate a first trigger signal; and
a second inverter circuit having an input coupled to the output of the first inverter circuit and an output configured to generate a second trigger signal;
wherein the first trigger signal is applied to the insulated gate of the embedded FET at the control gate terminal of the SCR.

4. The circuit of claim 3 ,
wherein the SCR is formed in a semiconductor substrate of a first conductivity type and includes a first region within the semiconductor substrate of the first conductivity type and having a higher doping level than the semiconductor substrate, and
wherein the second trigger signal is applied to the first region.

5. The circuit of claim 4 , wherein the semiconductor substrate further includes a second region of a second conductivity type opposite the first conductivity type, said second region forming a conduction terminal of the embedded FET.

6. The circuit of claim 5 , wherein the second region further forms the cathode terminal of the SCR.

7. The circuit of claim 1 , wherein the trigger circuit comprises:
a resistive-capacitive ESD detection circuit configured to generate an ESD detection signal;
an inverter circuit having an input coupled to receive the ESD detection signal and an output configured to generate the trigger signal.

8. The circuit of claim 1 , wherein the SCR is formed in a semiconductor substrate of a first conductivity type and includes a well of a second conductivity type opposite the first conductivity type, said well including a first region of the first conductivity type and having a higher doping level than the semiconductor substrate, said first region forming the anode terminal of the SCR.

9. The circuit of claim 8 , wherein the well further includes a second region of the second conductivity type having higher doping level than the well, and wherein the second region is a floating region.

10. The circuit of claim 1 , wherein the at least one trigger signal comprises a first trigger signal and a second trigger signal, and wherein the SCR is formed in a semiconductor substrate of a first conductivity type and includes a first region within the semiconductor substrate of the first conductivity type and having a higher doping level than the semiconductor substrate, and
wherein the first trigger signal is applied to the insulated gate of the embedded FET at the control gate terminal of the SCR and the second trigger signal is applied to the first region.

11. The circuit of claim 10 , wherein the first and second trigger signals are logical inversions.

12. The circuit of claim 10 , wherein the semiconductor substrate further includes a second region of a second conductivity type opposite the first conductivity type, said second region forming a conduction terminal of the embedded FET.

13. The circuit of claim 12 , wherein the second region further forms the cathode terminal of the SCR.

14. An electrostatic discharge (ESD) protection circuit, comprising:
a first power supply line;
a second power supply line;
a functional circuit electrically coupled for power supply to the first and second power supply lines;
an input/output pad coupled to the functional circuit;
a first protection diode connected between the input/output pad and the first power supply line;
a second protection diode connected between the input/output pad and the second power supply line;
a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, at least one trigger signal; and
a silicon controlled rectifier (SCR) having an anode terminal connected to the first power supply line and a cathode terminal connected to the second power supply line;
wherein the SCR further includes an embedded variable substrate resistor having an insulated gate which forms a control gate terminal coupled to receive said at least one trigger signal.

15. The ESD protection circuit of claim 14 , wherein a conduction terminal of the variable substrate resistor forms the cathode terminal of the SCR.

16. The circuit of claim 14 , wherein the trigger circuit comprises:
a resistive-capacitive ESD detection circuit configured to generate an ESD detection signal;
a first inverter circuit having an input coupled to receive the ESD detection signal and an output configured to generate a first trigger signal; and
a second inverter circuit having an input coupled to the output of the first inverter circuit and an output configured to generate a second trigger signal;
wherein the first trigger signal is applied to the insulated gate of the embedded variable substrate resistor at the control gate terminal of the SCR.

17. The circuit of claim 16 ,
wherein the SCR is formed in a semiconductor substrate of a first conductivity type and includes a first region within the semiconductor substrate of the first conductivity type and having a higher doping level than the semiconductor substrate, and
wherein the second trigger signal is applied to the first region.

18. The circuit of claim 17 , wherein the semiconductor substrate further includes a second region of a second conductivity type opposite the first conductivity type, said second region forming a conduction terminal of the variable substrate resistor.

19. The circuit of claim 18 , wherein the second region further forms the cathode terminal of the SCR.

20. The circuit of claim 14 , wherein the trigger circuit comprises:
a resistive-capacitive ESD detection circuit configured to generate an ESD detection signal;
an inverter circuit having an input coupled to receive the ESD detection signal and an output configured to generate the trigger signal.

21. The circuit of claim 14 , wherein the SCR is formed in a semiconductor substrate of a first conductivity type and includes a well of a second conductivity type opposite the first conductivity type, said well including a first region of the first conductivity type and having a higher doping level than the semiconductor substrate, said first region forming the anode

Assignees

• St Microelectronics Int Nv
• St Microelectronics Sa

Inventors

• Sithanandam Radhakrishnan
• Agarwal Divya
• Jimenez Jean
• Kar Malathi

Classifications

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/611

  using diodes as protective elements · CPC title

• H10D84/409

  Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors · CPC title