Plating methods for modular and/or ganged waveguides for automatic test equipment for semiconductor testing

Patent metadata

Field	Value
Publication number	US-10944148-B2
Application number	US-201615016143-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Feb 4, 2016
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

Embodiments described herein perform incisions along the direction of the long axis of the waveguide, thereby exposing a trench structure which can be readily plated. Once divided and plated, the individual cut pieces can then be secured together to restore the original waveguide structure. In this fashion, multiple cut pieces can be secured together and used as “building blocks” to create a modular solution which can be used to provide a number of different customizable waveguide structures. Thus, embodiments described herein can perform plating procedures in a less expensive manner while achieving the benefits of ganged waveguide structures. Moreover, embodiments described herein can offer a modular approach to ganged waveguide design thereby allowing for end-user flexibility in testing.

First claim

What is claimed is:

1. A method of plating a waveguide, said method comprising:
forming an incision along an outer portion of a waveguide structure;
dividing said waveguide structure into a plurality of portions using said incision to expose an inner surface of a first portion and a second portion of said plurality of portions of said waveguide structure;
plating a respective inner surface of said first portion and said second portion;
merging said first portion and said second portion together to restore said waveguide structure, wherein said first and second portions are sufficiently merged to facilitate substantial signal traversal through said waveguide structure;
joining a second waveguide structure to said waveguide structure to form a ganged waveguide structure, wherein the ganged waveguide structure comprises a plurality of waveguides disposed in parallel and adjacent to one another; and
attaching a common flange to said ganged waveguide structure, wherein said common flange is operable to secure one end of said plurality of waveguides to an electronic circuit.

2. The method of plating as described in claim 1 , wherein said forming an incision further comprises forming said incision along a longitudinal axis of said waveguide structure.

3. The method of plating as described in claim 1 , wherein said forming an incision further comprises selecting an incision point that divides said waveguide structure into two substantially equal portions.

4. The method of plating as described in claim 1 , wherein said dividing said waveguide structure further comprises forming a respective trench in said first and second portions having a width that extends from a location of said incision to an inner wall of said first and second portions.

5. The method of plating as described in claim 4 , wherein said plating further comprises applying a layer of material on top of said trench, said inner wall, and a top portion within said waveguide structure.

6. The method of plating as described in claim 5 , wherein said layer of material comprises copper.

7. The method of plating as described in claim 5 , wherein said layer of material comprises silver.

8. The method of plating as described in claim 6 , wherein said waveguide structure is fabricated from a plastic material using 3D printer technology.

9. A method of fabricating a waveguide, said method comprising:
forming an incision along an outer portion of a waveguide structure;
dividing said waveguide structure into a plurality of portions using said incision to thereby expose an inner surface of a first portion of said plurality of portions of said waveguide structure, wherein said inner surface comprises a trench formed therein having a width that extends from a location of said incision to an inner wall of said first portion;
plating said inner surface of said first portion with a conductive material;
joining a second waveguide structure to said waveguide structure to form a ganged waveguide structure, wherein the ganged waveguide structure comprises a plurality of waveguides disposed in parallel and adjacent to one another; and
attaching a common flange to said ganged waveguide structure, wherein said common flange is operable to secure one end of said plurality of waveguides to an electronic circuit.

10. The method of fabricating as described in claim 9 , wherein said forming an incision further comprises selecting an incision point dividing said waveguide structure into two substantially equal portions.

11. The method of fabricating as described in claim 9 , wherein said plating further comprises applying a thin layer of said conductive material on top of said trench, said inner wall of said first portion, and a top portion within said waveguide structure.

12. The method of fabricating as described in claim 11 , wherein said conductive material comprises copper.

13. The method of fabricating as described in claim 11 , wherein said conductive material comprises silver.

14. The method of fabricating as described in claim 9 , wherein said waveguide structure is fabricated using 3D printer technology.

15. The method of fabricating as described in claim 9 , wherein said first portion comprises mounting elements adapted to mount said first portion to a printed circuit board.

16. A method of fabricating a waveguide, said method comprising:
forming an incision along a longitudinal axis of a first waveguide structure;
dividing said waveguide structure into a plurality of portions using said incision to expose an inner surface of a first portion and a second portion of said plurality of portions of said waveguide structure and forming a respective trench in said first and second portions having a width that extends from a location of said incision to an inner wall of said first and second portions;
plating a respective inner surface of said first portion and said second portion;
merging said first portion and said second portion together to restore an original structure of said waveguide structure, wherein said first and second portions are sufficiently merged to facilitate substantial signal traversal through said waveguide structure;
joining a second waveguide structure to said first waveguide to form a ganged waveguide structure, wherein the ganged waveguide structure comprises a plurality of waveguides disposed in parallel and adjacent to one another; and
attaching a common flange to said ganged waveguide structure, wherein said common flange is operable to secure one end of said plurality of waveguides to an electronic circuit.

17. The method of fabricating as described in claim 16 , wherein said forming an incision further comprises selecting an incision point that divides said waveguide structure into two substantially equal portions.

18. The method of fabricating as described in claim 16 , wherein said plating comprises:
applying a first layer of material on top of said trench;
applying a second layer of material to said inner wall; and
applying a third layer of material to a top portion within said waveguide structure.

19. The method of fabricating as described in claim 18 , wherein said first, second and third layers comprise a same material.

20. The method of fabricating as described in claim 16 , wherein said waveguide is fabricated using 3D printer technology.

Assignees

• Advantest Corp

Inventors

• Lee Don
• Lam Daniel
• McAleenan Roger
• Miyao Kosuke

Classifications

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• H01P11/002 Primary

  Manufacturing hollow waveguides · CPC title

• H01P11/001 Primary

  Manufacturing waveguides or transmission lines of the waveguide type · CPC title

• H01P3/00

  Waveguides; Transmission lines of the waveguide type · CPC title

• G01R31/2886

  Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06) · CPC title