Array substrate, method for manufacturing array substrate, and display panel

Patent metadata

Field	Value
Publication number	US-10944083-B2
Application number	US-201816162013-A
Country	US
Kind code	B2
Filing date	Oct 16, 2018
Priority date	Mar 13, 2018
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

A method for manufacturing an array substrate, an array substrate and a display panel are provided herein. The method for manufacturing the array substrate includes: forming an inorganic layer on a base substrate; defining a preset region in a marginal region of the base substrate, and removing the inorganic layer in the preset region; and cutting the base substrate or the base substrate together with one or more layers on the base substrate in the preset region.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, comprising:
forming an inorganic layer on a base substrate;
defining a preset region in a marginal region of the base substrate, and removing the inorganic layer in the preset region; and
cutting the base substrate or the base substrate together with one or more layers on the base substrate in the preset region,
wherein the method further comprises: sequentially forming a first polyimide alignment film, a first interfacial barrier layer, and a second polyimide alignment film on the base substrate by a sputtering or vapor deposition process before forming the inorganic layer on the base substrate.

2. The method according to claim 1 , wherein the step of removing the inorganic layer in the preset region comprises:
applying resist on the inorganic layer;
exposing and developing the inorganic layer coated with the resist to remove the resist in the preset region; and
etching the inorganic layer by using a mask formed by the resist remaining in a non-preset region, to remove the inorganic layer in the preset region.

3. The method according to claim 1 , wherein the step of removing the inorganic layer in the preset region comprises:
forming an insulation layer on the inorganic layer, and applying resist on the insulation layer;
exposing and developing the insulation layer coated with the resist to remove the resist in the preset region; and
sequentially etching the insulation layer and the inorganic layer by using a mask formed by the resist remaining in a non-preset region, to remove the inorganic layer in the preset region.

4. The method according to claim 1 , wherein the step of removing the inorganic layer in the preset region comprises:
sequentially forming an insulation layer and a thin film encapsulation layer on the inorganic layer, and applying resist on the thin film encapsulation layer;
exposing and developing the thin film encapsulation layer coated with the resist to remove the resist in the preset region; and
sequentially etching the thin film encapsulation layer, the insulation layer and the inorganic layer by using a mask formed by the resist remaining in a non-preset region, to remove the inorganic layer in the preset region.

5. The method according to claim 1 , wherein the inorganic layer comprises a second interfacial barrier layer formed on the base substrate and a buffer layer formed on a side of the second interfacial barrier layer away from the base substrate.

6. The method according to claim 3 , wherein the insulation layer comprises a plurality of barrier dams and an anti-cracking dam disposed at an end of the insulation layer, and a patterning process of the barrier dams and the anti-cracking dam and the removal of the inorganic layer in the preset region are accomplished by one same process.

7. The method according to claim 6 , wherein the anti-cracking dam is located at an outer side of the plurality of barrier dams, and gaps are respectively provided between adjacent ones of the plurality of barrier dams and between the anti-cracking dam and the barrier dam adjacent thereto.

8. The method according to claim 7 , wherein the preset region is a region between a boundary of the base substrate and a boundary of the anti-cracking dam.

9. The method according to claim 3 , wherein the etching the insulation layer and the etching the inorganic layer are accomplished in a same process step; or
wherein the etching the insulation layer and the etching the inorganic layer are accomplished in different process steps.

10. The method according to claim 4 , wherein the etching the thin film encapsulation layer, the etching the insulation layer and the etching the inorganic layer are accomplished in a same process step; or
wherein the etching the thin film encapsulation layer, the etching the insulation layer and the etching the inorganic layer are accomplished in different process steps.

11. The method according to claim 2 , wherein the applying the resist on the inorganic layer comprises forming a resist layer having a uniform and flat upper surface by a spin coating process.

12. The method according to claim 11 , wherein the resist is positive or negative resist.

13. The method according to claim 1 , wherein the cutting the base substrate or the base substrate together with one or more layers on the base substrate comprises cutting the base substrate or the base substrate together with one or more layers on the base substrate by using laser.

14. The method according to claim 1 , wherein the cutting the base substrate or the base substrate together with one or more layers on the base substrate comprises cutting the base substrate or the base substrate together with one or more layers on the base substrate along a new side edge of the inorganic layer formed after the inorganic layer in the preset region is removed.

15. The method according to claim 4 , wherein the insulation layer comprises a plurality of barrier dams and an anti-cracking dam disposed at an end of the insulation layer, and a patterning process of the barrier dams and the anti-cracking dam and the removal of the inorganic layer in the preset region are accomplished by one same process.

16. The method according to claim 15 , wherein the anti-cracking dam is located at an outer side of the plurality of barrier dams, and gaps are respectively provided between adjacent ones of the plurality of barrier dams and between the anti-cracking dam and the barrier dam adjacent thereto.

17. The method according to claim 16 , wherein the preset region is a region between a boundary of the base substrate and a boundary of the anti-cracking dam.

18. An array substrate, manufactured by the method for manufacturing the array substrate according to claim 1 .

19. A display panel, comprising the array substrate according to claim 18 .

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Lv chong
• Tang Fuqiang
• Liu Xiaonan
• Zeng Yihong
• Song Ruinan
• Jin Fujiang

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W76/18 Primary

  Insulating materials, e.g. resins, glasses or ceramics · CPC title

• H10K59/873

  Encapsulations · CPC title

• H10K77/10 Primary

  Substrates, e.g. flexible substrates · CPC title