Semiconductor device for reading and outputting signal from a sensor

Patent metadata

Field	Value
Publication number	US-10938408-B2
Application number	US-202016858330-A
Country	US
Kind code	B2
Filing date	Apr 24, 2020
Priority date	Oct 26, 2017
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A semiconductor device includes a signal input circuit configured to select one of the plurality of differential sensor signals according to a channel selection signal; an amplifier circuit configured to amplify an output of the signal input circuit; and an analog-to-digital converter (ADC) configured to convert an output of the amplifier circuit into a digital value, wherein each of the plurality of sensor signals is a differential signals and the signal input circuit changes polarity of an output signal thereof according to a first chopping signal, and wherein the ADC includes a delta-sigma modulator configured to generate a bit stream from an output of the amplifier circuit; an output chopping circuit configured to adjust phase of the bit stream according to the first chopping signal; and a filter configured to filter an output of the output chopping circuit and to output the digital value.

First claim

What is claimed is:

1. A semiconductor device comprising:
a signal input circuit configured to select one of a plurality of sensor signals according to a channel selection signal;
an amplifier circuit configured to amplify an output of the signal input circuit; and
an analog-to-digital converter (ADC) configured to convert an output of the amplifier circuit into a digital value,
wherein each of the plurality of sensor signals is a differential signal and the signal input circuit changes polarity of an output signal thereof according to a first chopping signal,
wherein the ADC includes:
a delta-sigma modulator configured to generate a bit stream from an output of the amplifier circuit;
an output chopping circuit configured to adjust phase of the bit stream according to the first chopping signal; and
a filter configured to filter an output of the output chopping circuit and to output the digital value.

2. The semiconductor device of claim 1 , wherein the signal input circuit includes:
a chopping switch;
a chopping switch controller configured to control the chopping switch according to the channel selection signal and the first chopping signal; and
a dummy switch controlled by the channel selection switch and coupled to the chopping switch.

3. The semiconductor device of claim 2 , wherein the chopping switch includes a first switch element and the dummy switch includes a second switch element, wherein the first switch element and the second switch element are switched complementarily.

4. The semiconductor device of claim 1 , wherein the amplifier circuit includes:
an input capacitor;
an amplifier including an input terminal coupled to a first node of the input capacitor, and an output terminal, and configured to amplify a signal provided at the input terminal and to provide an amplified signal at the output terminal; and
a first feedback circuit including a feedback capacitor and configured to negatively feedback the amplified signal to the input terminal,
wherein a gain of the amplifier circuit is determined by capacitance ratio of the input capacitor and the feedback capacitor.

5. The semiconductor device of claim 4 , wherein the input terminal includes differential input terminals and the output terminal includes differential output terminals,
wherein the input capacitor includes a first input capacitor and a second input capacitor coupled to the differential input terminals respectively,
wherein the feedback capacitor includes a first feedback capacitor and a second feedback capacitor coupled to the differential input terminals respectively,
wherein the amplifier circuit further comprises a first chopping circuit configured to change connecting paths between the signal input circuit and the first input capacitor and the second input capacitor according to the second chopping signal and a second chopping circuit to change connecting paths between the differential output terminals and the first feedback capacitor and the second feedback capacitor according to the second chopping signal, and
wherein the amplifier changes polarity of signals therein provided to the differential output terminals according to the second chopping signal.

6. The semiconductor device of claim 5 , wherein the amplifier circuit includes a second feedback circuit that positively feedbacks an output of the amplifier to a second node of the input capacitor through an impedance boosting capacitor,
wherein the impedance boosting capacitor includes a first impedance boosting capacitor coupled to the first input capacitor and a second impedance boosting capacitor coupled to the second input capacitor, and
wherein the amplifier circuit further comprises a third chopping circuit configured to change coupling paths between the differential output terminals and the first impedance boosting capacitor and the second impedance boosting capacitor.

7. The semiconductor device of claim 4 , wherein the amplifier circuit further includes a third feedback circuit configured to generate a ripple suppression signal from an output of the amplifier, and the amplifier is configured to perform an amplification operation with the ripple suppression signal and a signal provided at the input terminal.

8. The semiconductor device of claim 1 , wherein a period of the first chopping signal is greater than time required to perform an analog-to-digital conversion operation at the ADC.

9. The semiconductor device of claim 1 , wherein the delta-sigma modulator is configured to be reset according to a reset signal enabled every half-period of the first chopping signal and an edge of the reset signal is aligned with an edge of the first chopping signal.

10. The semiconductor device of claim 1 , wherein the filter includes a sinc filter filtering an output of the output chopping circuit and a finite impulse response (FIR) filter filtering an output of the sinc filter and providing the digital value.

11. The semiconductor device of claim 10 , wherein the FIR filter generates the digital value by calculating a moving average of values output from the sinc filter.

12. The semiconductor device of claim 1 , wherein the delta-sigma modulator includes a first capacitor for sampling an output of the amplifier circuit and a second capacitor for sampling an analog value corresponding to the bit stream, and wherein gain of the ADC is determined by a ratio of capacitances of the first capacitor and the second capacitor.

13. The semiconductor device of claim 12 , wherein the delta-sigma modulator further includes an integrating filter for integrating an output of the sampling circuit and a comparator for generating the bit stream from an output of the integrating filter.

14. The semiconductor device of claim 12 , wherein capacitance of the first capacitor or capacitance of the second capacitor is controlled according to the bit stream or the digital value.

15. The semiconductor device of claim 14 , wherein gain of the amplifier circuit is controlled according to the bit stream or the digital value.

Assignees

• Seoul Nat Univ R&Db Foundation

Inventors

• Jun Jaehoon
• Rhee Cyuyeol
• Kim Suhwan

Classifications

• H03M3/504

  the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03M3/368

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/34 Primary

  by chopping · CPC title

• H03F3/393

  with field-effect devices · CPC title