Low noise amplifier circuit

Patent metadata

Field	Value
Publication number	US-10148237-B2
Application number	US-201715402502-A
Country	US
Kind code	B2
Filing date	Jan 10, 2017
Priority date	Jan 15, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A semiconductor circuit comprising an input block having a first chopper providing a chopped voltage signal, a first transconductance converting said chopped voltage signal into a chopped current signal, a second chopper providing a demodulated current signal, a current integrator having an integrating capacitor providing a continuous-time signal, a first feedback path comprising: a sample-and-hold block and a first feedback block, the first feedback path providing a proportional feedback signal upstream of the current integrator. The amplification factor is at least 2. Charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period. Each chopper operates at a chopping frequency. The sample-and-hold-block operates at a sampling frequency equal to an integer times the chopping frequency.

First claim

The invention claimed is:

1. A semiconductor circuit, comprising:
an input block comprising a first chopper for providing a chopped input voltage signal indicative of a voltage signal to be amplified;
a first transconductance arranged downstream of the first chopper and adapted for receiving said chopped voltage signal and adapted for converting said chopped voltage signal into a chopped current signal;
a second chopper arranged downstream of the first transconductance adapted for providing a demodulated current signal;
a current integrator arranged downstream of the second chopper, the current integrator comprising an integrating capacitor for storing an integrated signal and being adapted for providing a continuous-time signal;
a first feedback path comprising:

a sample-and-hold block arranged downstream of the current integrator and adapted for receiving the continuous-time signal and for sampling said signal using a sampling signal thereby providing a sampled signal, and for providing a zero-order-hold voltage signal proportional to said sampled signal;
a first feedback block arranged downstream of the sample-and-hold block, the first feedback path being adapted for providing a first feedback signal proportional to the zero-order-hold signal according to a predefined proportionality factor, the first feedback signal being provided to the current integrator or upstream of the current integrator;
and wherein the semiconductor circuit is configured such that an amplitude ratio of the continuous-time signal and the voltage signal to be amplified is at least 2.0;
and wherein the first feedback block is adapted for providing the feedback signal such that, for a chopped input signal equal to zero, a charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period of the sampling signal, in such a way that the charge is completely removed at the end of the single sampling period;
and wherein each of the first and second chopper is adapted to be operated at a chopping frequency, and the sample-and-hold-block is adapted to be operated at a sampling frequency, wherein the sampling frequency is equal to the chopping frequency or equal to an integer times the chopping frequency.

2. The semiconductor circuit according to claim 1 , wherein the first feedback path is arranged in one of the following ways:
i) wherein the first feedback block comprises or is a second transconductance adapted for providing a current feedback signal which is fed back between an output of the second chopper and an input of the current integrator;
ii) wherein the feedback block comprises or consists of a scaler for providing a voltage feedback signal, and the voltage feedback signal is fed back upstream of the first chopper;
iii) wherein the feedback block comprises a second transconductance for providing a current feedback signal proportional to the zero-order-hold signal, and the current feedback signal is fed back upstream of the first chopper;
iv) wherein the feedback block comprises a third chopper and second transconductance connected in series, for providing a chopped current feedback signal, the third chopper operable at the chopping frequency, and wherein the chopped current feedback signal is fed back between an output of the first transconductance and an input of the second chopper;
v) wherein the feedback block comprises a third chopper and a second transconductance connected in series, for providing a chopped current feedback signal, the third chopper operable at the chopping frequency, and wherein the chopped current feedback signal is fed back to an internal node of the first transconductance;
vi) wherein the feedback block comprises a third chopper and a scaler connected in series for providing a chopped voltage feedback signal, the third chopper operable at the chopping frequency, and the chopped voltage feedback signal is fed back between an output of the first chopper and an input of the first transconductance.

3. The semiconductor circuit according to claim 1 , wherein the sampling frequency is twice the chopping frequency.

4. The semiconductor circuit according to claim 1 , wherein the sampling frequency is equal to the chopping frequency.

5. The semiconductor circuit according to claim 1 , further comprising, a third chopper arranged downstream of the current integrator and operable at the chopping frequency,
and further comprising: a second feedback path for removing DC-offset and flicker noise, the second feedback path being adapted for providing a second feedback signal to the current integrator or upstream of the current integrator, the second feedback path comprising:
the third chopper, and
a filter arranged downstream of the third chopper, the filter having a transfer function comprising at least one integration and a factor (1+Z −1 ).

6. The semiconductor circuit according to claim 1 , further comprising a second feedback path for removing DC-offset, the second feedback path being adapted for providing a second feedback signal to the current integrator or upstream of the current integrator, the second feedback path comprising:
a second sampler operable at a second sample frequency, and a fourth chopper arranged downstream of the second sampler, the fourth chopper operable at the chopping frequency, and
a filter arranged downstream of the fourth chopper, the filter having a transfer function comprising at least one integration and a factor (1+Z −1 ), and
wherein the second sampling frequency is equal to twice the chopping frequency.

7. The semiconductor circuit according to claim 1 ,
wherein the input block is further adapted for receiving the voltage signal to be amplified from one or two external pins or from a voltage source inside the integrated circuit,
or wherein the input block further comprises an impedance or transimpedance arranged upstream or downstream of the first chopper and is further adapted for receiving a continuous-time current signal from an external pin or from a current source inside the integrated circuit,
or wherein the input block further comprises a transducer of the kind that converts a physical signal or excitation into a voltage signal, the transducer being arranged upstream of the first chopper for providing the voltage signal to be amplified in response to the physical signal or excitation;
or wherein the input block further comprises a transducer of the kind that requires a biasing signal and provides a voltage signal indicative of a physical quantity, the transducer being arranged upstream of the first chopper for providing the voltage signal to be amplified in response to the physical quantity.

8. The semiconductor circuit according to claim 1 , wherein at least all components downstream of the first chopper are integrated on a single semiconductor die.

9. A sensor device comprising:
at least one sensor element or at least one transducer or at least one impedance or transimpedance for providing at least one voltage signal to be amplified;
a semiconductor circuit according to claim 1 , arranged for amplifying said at least one voltage signal.

10. The sensor device according to claim 9 , further comprising:
an analog-to-digital convertor for converting the amplified voltage signal;
a processor for digitally processing the digitized signal.

11. The sensor device according to claim 9 , wherein the at least one transducer comprises at least one Hall sensor.

12. The sensor device according to claim 9 , wherein the sensor device is a position sensor device or an electronic compass.

13. A semiconductor circuit, comprising:

Assignees

• Melexis Tech Sa

Inventors

• Raman Johan
• Rombouts Pieter

Classifications

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title

• H03F2203/45564

  the IC comprising one or more extra current sources · CPC title

• H03F2203/45472

  the CSC comprising one or more diodes · CPC title

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F2200/156

  One or more switches are realised in the feedback circuit of the amplifier stage · CPC title