Back power protection circuit

Patent metadata

Field	Value
Publication number	US-10938200-B2
Application number	US-201715443161-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Sep 11, 2014
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

First claim

We claim:

1. An apparatus comprising:
a transceiver to couple to a device external to the apparatus;
a power-up detector to receive an internal power supply; and
a protection circuit,
wherein the protection circuit is to bias the transceiver using power from the internal power supply via the power-up detector, in response to the internal power supply being available,
wherein the transceiver comprises a transmitter, and
wherein the transmitter comprises:
a first p-type transistor; and
a second p-type transistor coupled in series with the first p-type transistor.

2. The apparatus of claim 1 , wherein the protection circuit is to cause the transceiver to be in a high impedance state using power from the device external to the apparatus, in response to the internal power supply being unavailable to bias the transceiver.

3. The apparatus of claim 2 , wherein the protection circuit is to cause the transceiver to be in the high impedance state by tri-stating the transceiver.

4. The apparatus of claim 1 , wherein the protection circuit comprises:
a sense circuit to sense availability of the internal power supply.

5. The apparatus of claim 2 , wherein the power from the device is received in the apparatus via a first signal line and a second signal line, and wherein the protection circuit comprises:
a sense circuit to sense attributes of signals transmitted over the first signal line and the second signal line.

6. The apparatus of claim 5 , wherein the sense circuit is to sense an availability of the power from the device external to the apparatus.

7. The apparatus of claim 2 , wherein:
the protection circuit is to select one of the power from the internal power supply to bias the transceiver or the power from the device external to the apparatus to cause the transceiver to be in the high impedance state, based at least in part on:
availability of the internal power supply, and
availability of power from the device external to the apparatus.

8. The apparatus of claim 2 , wherein:
the protection circuit is to bias one or more transistors within the protection circuit using power from the device external to the apparatus, in response to the internal power supply being unavailable.

9. The apparatus of claim 2 , further comprising:
a battery,
wherein the internal power supply is unavailable in response to a charge level of the battery being exhausted or in response to the battery being turned off.

10. The apparatus of claim 1 , wherein the transceiver is one of:
a USB compliant transceiver;
an HDMI compliant transceiver; or
an Interface connected to UICC element (Sim card) in NFC application.

11. The apparatus of claim 2 , wherein the protection circuit comprises:
a bias generation circuit to:
selectively receive the internal power supply and/or the power from the device external to the apparatus, and
generate bias voltage for the transceiver from one of the internal power supply or the power from the device external to the apparatus.

12. The apparatus of claim 2 , wherein the transmitter is to provide a first voltage signaling and a second voltage signaling to the device external to the apparatus.

13. The apparatus of claim 12 , wherein the transmitter comprises:
a first n-type transistor coupled in series with the second p-type transistor;
a second n-type transistor coupled in series with the first n-type transistor; and
a third p-type transistor coupled to the first and second n-type transistors.

14. The apparatus of claim 13 , wherein the protection circuit is to supply bias voltages to at least two of the first p-type, second p-type, third p-type, first n-type, and second n-type transistors.

15. A system comprising:
a memory;
a processor coupled to the memory, the processor including:
a transceiver to couple to a charging device external to the system; and
a back power protection circuit to cause the transceiver to tri-state based on the charging device being coupled to the transceiver and one or more internal power supply of the system is inadequate or unavailable to bias the transceiver, wherein the transceiver comprises a transmitter, and wherein the transmitter comprises:
a first p-type transistor; and
a second p-type transistor coupled in series with the first p-type transistor; and

a wireless interface to facilitate the processor to communicate with another device.

16. The system of claim 15 , further comprising:
a display interface to display content processed by the processor.

17. The system of claim 15 , wherein the back power protection circuit is to bias the transceiver with power from the one or more internal power supply, based on the one or more internal power supply of the system being adequate to bias the transceiver.

18. An apparatus comprising:
means for receiving one or both of an internal power supply and external power supply from a device that is external from the apparatus;
means for communicating, by a transceiver of the apparatus, with the device;
means for biasing the transceiver using power from the internal power supply, in response to the internal power supply being available; and
means for causing the transceiver to be in a high impedance state using power from the device external to the apparatus, in response to the internal power supply being unavailable to bias the transceiver and in response to the device being coupled to the apparatus, wherein the transceiver comprises a transmitter, and wherein the transmitter comprises:
a first p-type transistor; and
a second p-type transistor coupled in series with the first p-type transistor.

19. The apparatus of claim 18 , further comprising:
means for sensing an availability of the internal power supply; and
means for sensing an availability of the power from the device external to the apparatus.

20. The apparatus of claim 18 , wherein:
the internal power supply is unavailable in response to a charge level of a battery being exhausted or in response to the battery being turned off.

21. An apparatus comprising:
a Universal Serial Bus (USB) compliant transceiver to couple to a device external to the apparatus;
a first circuit to detect presence or absence of one or more power supply voltages on one or more power supply rails, wherein the one or more power supply rails are coupled to the transceiver; and
a second circuit to change output characteristic of the transceiver based on the device being coupled to the transceiver and based on the detection by the first circuit of absence of the one or more power supply voltages.

22. The apparatus of claim 21 , wherein the second circuit comprises: a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of one or more signal lines coupled to the transceiver.

23. The apparatus of claim 22 , wherein the second circuit is to sense signal attributes of the one or more signals.

24. The apparatus of claim 21 , wherein the device external to the apparatus comprises a battery.

25. The apparatus of claim 21 , wherein:
the transceiver comprises a transmitter which comprises:
a first p-type transistor;
a second p-type transistor coupled in series with the first p-type transistor;
a first n-type transistor coupled in series with the second p-type transistor;
a second n-type transistor coupled in series with the first n-type transistor; and
a third

Assignees

• Intel Corp

Inventors

• Srivastava Amit Kumar
• Ns Karthik
• Sharma Raghavendra Devappa
• Nedalgi Dharmaray
• Bhilawadi Prasad

Classifications

• G06F1/3212

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• H02H3/18 Primary

  responsive to reversal of direct current · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H04B1/38

  Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title