Integrated circuit devices and fabrication techniques

Patent metadata

Field	Value
Publication number	US-10325927-B2
Application number	US-201715586195-A
Country	US
Kind code	B2
Filing date	May 3, 2017
Priority date	Apr 4, 2013
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

First claim

The invention claimed is:

1. A device, comprising:
a substrate;
a first fin extending from a first surface of the substrate, the first fin including:
a source, a channel, and a drain of a first p-type Fin Field Effect Transistor (FinFET); and
a source and a channel of a second p-type FinFET, the second p-type FinFET sharing the drain of the first p-type FinFET, the first and second p-type FinFETs aligned along a first axis; and

a second fin extending from the first surface of the substrate, the second fin including:
a source, a channel, and a drain of a first n-type FinFET; and
a drain and a channel of a second n-type FinFET, the second n-type FinFET sharing the source of the first n-type FinFET, the first and second n-type FinFETs are aligned along the first axis and spaced from the first and second p-type FinFETs.

2. The device of claim 1 , further comprising:
a third fin extending from the first surface of the substrate, the third fin abutting the second fin and being aligned along a second axis, the second axis being transverse to the first axis, the third fin including a source and a channel of a third n-type FinFET, the third n-type FinFET sharing the drain of the first n-type FinFET; and
a fourth fin extending from the first surface of the substrate, the fourth fin abutting the second fin and being aligned along the second axis and spaced apart from the third fin, the fourth fin including a source and a channel of a fourth n-type FinFET, the fourth n-type FinFET sharing the drain of the second n-type FinFET.

3. The device of claim 2 , wherein the second fin, the third fin, and the fourth fin are portions of a single contiguous layer.

4. The device of claim 2 , wherein the third n-type FinFET further includes a first gate structure, which includes a first portion and a second portion separated by a space, the first portion located on a first side of the third fin and the second portion arranged on a second side of the third fin such that the first portion and the second portion are laterally positioned relative to the channel of the third n-type FinFET and are aligned along the first axis.

5. The device of claim 4 , wherein the space contains an insulator.

6. The device of claim 4 , wherein the fourth n-type FinFET further includes a second gate structure, which includes a third portion and a fourth portion separated by a second space, the third portion located on a first side of the fourth fin and the fourth portion arranged on a second side of the fourth fin such that the third portion and the fourth portion are laterally positioned relative to the channel of the fourth n-type FinFET and are aligned along the first axis.

7. The device of claim 6 , wherein the space contains an insulator.

8. The device of claim 1 , wherein the first and the second n-type FinFETs and the first and the second p-type FinFETs are cross-coupled inverters.

9. The device of claim 1 , wherein a portion of the substrate corresponding to the channel of the first p-type FinFET, the second p-type FinFET, the first n-type FinFET, or the second n-type FinFET is fully or partially depleted.

10. A device, comprising:
a substrate having a surface;
a first fin extending from the surface of the substrate;
a second fin extending from the surface of the substrate;
a first transistor aligned along a first axis and including:
a first source in the first fin;
a first channel in the first fin; and
a first drain in the first fin;

a second transistor aligned along the first axis and including:
a second source in the first fin;
a second channel in the first fin; and
the first drain;

a third transistor aligned along a second axis that is substantially parallel to the first axis and including:
a third source in the second fin;
a third channel in the second fin; and
a second drain in the second fin;

a fourth transistor aligned along the second axis and including:
the third source;
a fourth channel in the second fin; and
a third drain in the second fin.

11. The device of claim 10 , wherein the first and second transistors are p-type and the third and fourth transistors are n-type.

12. The device of claim 10 , further comprising a third fin extending from the surface of the substrate, the third fin abutting the second fin.

13. The device of claim 12 , further comprising a fifth transistor aligned along a third axis that is transverse to the second axis, the fifth transistor including:
a fourth source in the third fin;
a fifth channel in the third fin; and
the second drain.

14. The device of claim 13 , further comprising a fourth fin extending from the surface of the substrate, the fourth fin abutting the second fin.

15. The device of claim 14 , further comprising a sixth transistor aligned along a fourth axis that substantially parallel to and spaced apart from the third axis, the sixth transistor including:
a fifth source in the third fin;
a sixth channel in the third fin; and
the third drain.

16. A device, comprising:
a substrate having a surface;
a first fin extending from the surface of the substrate, the first fin including:
a first source of a first transistor;
a second source of a second transistor;
a first channel of the first transistor;
a second channel of the second transistor; and
a first drain shared by the first and second transistor;

a second fin extending from the surface of the substrate, the second fin being substantially parallel to and spaced apart from the first fin, the second fin including:
a third channel of a third transistor; and
a fourth channel of a fourth transistor;
a second drain of the third transistor;
a third drain of the fourth transistor; and
a third source shared by the third transistor and the fourth transistor.

17. The device of claim 16 , further comprising:
a third fin extending from the surface of the substrate, the third fin abutting the second fin and extending in a direction transverse to the second fin; and
a fourth fin extending from the surface of the substrate, the fourth fin abutting the second fin and being substantially parallel to and spaced apart from the third fin.

18. The device of claim 17 , wherein:
the third fin includes:
a fourth source of a fifth transistor; and
a fifth channel of the fifth transistor;

the fourth fin includes:
a fifth source of a sixth transistor; and
a sixth channel of the sixth transistor;

the second drain is shared by the fifth transistor; and
the third drain is shared by the sixth transistor.

19. The device of claim 16 , wherein the second fin, the third fin, and the fourth fin are portions of a single contiguous layer.

Assignees

• St Microelectronics Inc

Inventors

• Zhang John H

Classifications

• H10P30/22

  using masks · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L21/266

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic