Handling Memory Requests
US-2026056768-A1 · Feb 26, 2026 · US
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Landers Mark patents
Landers Mark is listed as an inventor on 34 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Landers Mark |
| Total patents | 34 |
| First publication | Oct 5, 2017 |
| Latest publication | Feb 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Handling memory requests
US-12481521-B2 · Nov 25, 2025 · US
Executing Memory Requests Out of Order
US-2025335201-A1 · Oct 30, 2025 · US
Distributed System Level Cache
US-2025291727-A1 · Sep 18, 2025 · US
Executing memory requests out of order
US-12353883-B2 · Jul 8, 2025 · US
Distributed system level cache
US-12321271-B2 · Jun 3, 2025 · US
Memory interface having multiple snoop processors
US-2025156328-A1 · May 15, 2025 · US
Memory interface having multiple snoop processors
US-12235767-B2 · Feb 25, 2025 · US
Handling memory requests
US-2024230612-A1 · Jul 11, 2024 · US
Distributed system level cache
US-2024160571-A1 · May 16, 2024 · US
Recent patents
Latest publications not already listed above.
Handling memory requests
US-11941430-B2 · Mar 26, 2024 · US
Data coherency manager with mapping between physical and virtual address spaces
US-11914514-B2 · Feb 27, 2024 · US
Memory Interface Having Multiple Snoop Processors
US-2023393983-A1 · Dec 7, 2023 · US
Memory interface having multiple snoop processors
US-11734177-B2 · Aug 22, 2023 · US
Handling Memory Requests
US-2023119485-A1 · Apr 20, 2023 · US
Handling memory requests
US-11537427-B2 · Dec 27, 2022 · US
Memory interface between physical and virtual address spaces
US-11372777-B2 · Jun 28, 2022 · US
Memory Interface Having Multiple Snoop Processors
US-2021390052-A1 · Dec 16, 2021 · US
Memory interface having multiple snoop processors
US-11132299-B2 · Sep 28, 2021 · US
Data coherency manager with mapping between physical and virtual address spaces
US-2021294744-A1 · Sep 23, 2021 · US
Data coherency manager with mapping between physical and virtual address spaces
US-11030103-B2 · Jun 8, 2021 · US
Executing Memory Requests Out of Order
US-2021157596-A1 · May 27, 2021 · US
Memory Interface Between Physical and Virtual Address Spaces
US-2021149822-A1 · May 20, 2021 · US
Handling Memory Requests
US-2021132984-A1 · May 6, 2021 · US
Memory interface between physical and virtual address spaces
US-10936509-B2 · Mar 2, 2021 · US
Executing memory requests out of order
US-10929138-B2 · Feb 23, 2021 · US
Handling memory requests
US-10908945-B2 · Feb 2, 2021 · US
Memory Interface Having Multiple Snoop Processors
US-2019266091-A1 · Aug 29, 2019 · US
Memory Interface Between Physical and Virtual Address Spaces
US-2019266101-A1 · Aug 29, 2019 · US
Data Coherency Manager with Mapping Between Physical and Virtual Address Spaces
US-2019266092-A1 · Aug 29, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Imagination Tech Ltd | 34 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0831 | 26 |
| G06F12/1063 | 19 |
| Y02D10/00 | 16 |
| G06F2212/60 | 16 |
| G06F12/1018 | 15 |