Array substrate, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-10935857-B2
Application number	US-201816082709-A
Country	US
Kind code	B2
Filing date	Jan 25, 2018
Priority date	Jul 21, 2017
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

The present disclosure provides an array substrate, a manufacturing method of an array substrate, and a display device. The array substrate includes: a base substrate; a first signal line, extending in a first direction and located on the base substrate; a second signal line, extending in a second direction and located on a side of the first signal line away from the base substrate and insulated with the first signal line, the first direction and the second direction crossing with each other. A side of the first signal line facing the second signal line is provided with a groove, the groove is located at a crossing region between the first signal line and the second signal line, in the crossing region, an otherographic projection of the second signal line on the base substrate completely falls into an orthographic projection of the groove on the base substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a first signal line, extending in a first direction and located on the base substrate;
a second signal line, extending in a second direction, located on a side of the first signal line away from the base substrate, and insulated with the first signal line, the first direction and the second direction crossing with each other,
wherein a side of the first signal line facing the second signal line is provided with a groove, the groove is located at a crossing region between the first signal line and the second signal line, at the crossing region, an orthographic projection of the second signal line on the base substrate completely falls into an orthographic projection of the groove on the base substrate.

2. The array substrate according to claim 1 , wherein the first signal line further comprises a first portion and a second portion which are located on two sides of the groove, the first portion comprises a first connection portion connected with the groove, the second portion comprises a second connection portion connected with the groove, in the second direction, a maximum size of the groove is greater than a size of at least one selected from the group consisting of the first connection portion and the second connection portion.

3. The array substrate according to claim 1 , further comprising:
a first insulating layer, located between the first signal line and the second signal line.

4. The array substrate according to claim 3 , further comprising:
a second insulating layer, located between the first signal line and the second signal line,
wherein an orthographic projection of the second insulating layer on the base substrate and an orthographic projection of the groove on the base substrate are completely overlapped, in a direction perpendicular to the base substrate, a thickness of the second insulating layer is equal to a depth of the groove, so as to compensate a height difference between a surface of the first signal line or the first insulating layer away from the base substrate and the base substrate due to the groove.

5. The array substrate according to claim 4 , wherein the second insulating layer is located between the first insulating layer and the first signal line, or between the first insulating layer and the second signal line.

6. The array substrate according to claim 1 , wherein, in a direction perpendicular to the base substrate, a ratio of a depth of the groove and a thickness of a portion of the first signal line excluding the groove is less than 1:2.

7. The array substrate according to claim 1 , wherein one of the first signal line and the second signal line is a scanning line, and the other one of the first signal line and the second signal line is a data line.

8. A display device, comprising the array substrate according to claim 1 .

9. A manufacturing method of an array substrate, comprising:
forming a first signal line extending in a first direction on a base substrate;
forming a groove at a side of the first signal line away from the base substrate;
forming a second signal line extending in a second direction above the first signal line, the second signal line and the first signal line being insulated with each other, the first direction and the second direction crossing with each other,
wherein the groove is located at a crossing region between the first signal line and the second signal line, at the crossing region, an orthographic projection of the second signal line on the base substrate completely falls into an orthographic projection of the groove on the base substrate.

10. The manufacturing method of the array substrate according to claim 9 , wherein forming the groove comprises:
forming a first insulating layer on the first signal line;
etching the first insulating layer at the crossing region to form a via hole to expose the first signal line; and
etching an exposed portion of the first signal line to form the groove.

11. The manufacturing method of the array substrate according to claim 10 , wherein, before forming the second signal line, the manufacturing method further comprises:
filling the groove and the via hole with an insulating material, wherein the groove is filled with the insulating material to form a second insulating layer, a surface of the second insulating layer is flushed with a surface of the first signal line, and the via hole is filled with the insulating material to make a thickness of the first insulating layer uniform.

12. The manufacturing method of the array substrate according to claim 9 , wherein forming the groove comprises:
forming a photoresist pattern on the first signal line; and
etching the first signal line by using the photoresist pattern as a mask to form the groove.

13. The manufacturing method of the array substrate according to claim 12 , wherein, before forming the second signal line, the manufacturing method further comprises:
filling the groove with an insulating material to form a second insulating layer, a surface of the second insulating layer being flushed with a surface of the first signal line; and
forming a first insulating layer on the first signal line and the second insulating layer.

14. The manufacturing method of the array substrate according to claim 10 , wherein the first signal line further comprises a first portion and a second portion which are located on two sides of the groove, the first portion comprises a first connection portion connected with the groove, the second portion comprises a second connection portion connected with the groove, wherein, forming the first signal line comprises:
patterning the first signal line to make a maximum size of the first signal line at a position where the groove is to be formed greater than a size of at least one selected from the group consisting of the first connection portion and the second connection portion in the second direction.

15. The manufacturing method of the array substrate according to claim 9 , wherein the first signal line and the groove are patterned by one mask plate, and formed by a half tone mask process.

16. The manufacturing method according to claim 12 , wherein, before forming the second signal line, the manufacturing method further comprises:
forming a first insulating layer on the first signal line, a portion of the first insulating layer which is located at the groove being formed as a concave portion; and
filling the concave portion with an insulating material to form a second insulating layer, a surface of the second insulating layer being flushed with a surface of the first insulating layer.

17. The manufacturing method of the array substrate according to claim 9 , wherein, in a direction perpendicular to the base substrate, a ratio of a depth of the groove and a thickness of a portion of the first signal line excluding the groove is less than 1:2.

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Zhang Guolin
• Cheng Jiuyang
• Zou Jiahong
• Xiao Wenhao
• Li Junliang
• Ma Yihong

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title