Electronic device having a delay locked loop, and memory device having the same

Patent metadata

Field	Value
Publication number	US-2016156342-A1
Application number	US-201514955051-A
Country	US
Kind code	A1
Filing date	Dec 1, 2015
Priority date	Dec 1, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal. The delay control circuit is configured to generate the delay control code based on the clock signal and the first output clock signal.

First claim

1 . An electronic device, comprising:
a first duty cycle correction circuit configured to detect a duty cycle error of a clock signal by performing a time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the detected duty cycle error of the clock signal; a delay line configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code; a second duty cycle correction circuit configured to receive a first output clock signal through a feedback loop, to detect a duty cycle error of the first output clock signal by performing an integration operation on the first output clock signal, and to generate a second output clock signal by adjusting a duty cycle of the delayed corrected clock signal based on the detected duty cycle error of the first output clock signal; and a delay control circuit configured to generate the delay control code based on the clock signal and the first output clock signal.

2 . The electronic device of claim 1 , wherein the first duty cycle correction circuit includes:
a duty cycle error detection circuit configured to generate a sign signal, which indicates a longer period between a high level period of the clock signal and a low level period of the clock signal, and a duty error digital code, which corresponds to a difference between a length of the high level period of the clock signal and a length of the low level period of the clock signal; a phase align circuit configured to output one of the clock signal and an inverted clock signal, which corresponds to an inverted version of the clock signal, as a first internal clock signal, based on a logic level of the sign signal, and to generate a second internal clock signal by delaying the other one of the clock signal and the inverted clock signal by an amount of time corresponding to half of the duty error digital code; and a clock synthesis circuit configured to generate the corrected clock signal, which toggles at each rising edge of the first internal clock signal and each rising edge of the second internal clock signal.

3 . The electronic device of claim 2 , wherein the duty cycle error detection circuit includes:
a first digital code generator configured to generate a high digital code and a low digital code, which correspond to the length of the high level period of the clock signal and the length of the low level period of the clock signal, respectively, to determine a longer period and a shorter period between the high level period of the clock signal and the low level period of the clock signal based on the high digital code and the low digital code, to generate the sign signal indicating the longer period of the clock signal, and to output one of the high digital code and the low digital code, which corresponds to the shorter period of the clock signal, as a first digital code; a clock delay circuit configured to generate a delayed clock signal by delaying the clock signal by an amount of time corresponding to the first digital code; and a second digital code generator configured to generate the duty error digital code, which corresponds to a length from a start of the longer period of the delayed clock signal to an end of the longer period of the clock signal, based on the logic level of the sign signal, wherein the longer period of the delayed clock signal is the longer of a high level period of the delayed clock signal and a low level period of the delayed clock signal, and wherein the longer period of the clock signal is the longer of the high level period of the clock signal and the low level period of the clock signal.

4 . The electronic device of claim 3 , wherein the first digital code generator generates the high digital code and the low digital code by performing the time-to-digital conversion on the length of the high level period of the clock signal and the length of the low level period of the clock signal, respectively, based on a first unit delay, and
wherein the second digital code generator generates the duty error digital code by performing the time-to-digital conversion on the length from the start of the longer period of the delayed clock signal to the end of the longer period of the clock signal, based on a second unit delay smaller than the first unit delay.

5 - 6 . (canceled)

7 . The electronic device of claim 3 , wherein the first duty cycle correction circuit further includes:
a multiplexer configured to output one of the clock signal and the corrected clock signal in response to a bypass signal, wherein the first digital code generator activates the bypass signal when the high digital code is identical to the low digital code.

8 . The electronic device of claim 3 , wherein the first duty cycle correction circuit further includes:
an OR gate configured to perform an OR operation on a first control signal and a second control signal to generate a bypass signal; and a multiplexer configured to output one of the clock signal and the corrected clock signal in response to the bypass signal, wherein the first digital code generator activates the first control signal when the high digital code is identical to the low digital code, and the second digital code generator activates the second control signal when the duty error digital code is smaller than a threshold code.

9 . The electronic device of claim 2 , wherein the phase align circuit includes:
a phase splitter configured to receive the clock signal, and to output the clock signal and the inverted clock signal in synchronization with each other; a first path selector configured, based on the logic level of the sign signal, to output one of the clock signal and the inverted clock signal as the first internal clock signal and to output the other one of the clock signal and the inverted clock signal as a third internal clock signal; a clock delay circuit configured to generate the second internal clock signal by delaying the third internal clock signal for a time corresponding to half of the duty error digital code; and a second path selector configured, based on the logic level of the sign signal, to output one of the first internal clock signal and the second internal clock signal through a first output electrode and to output the other one of the first internal clock signal and the second internal clock signal through a second output electrode.

10 . The electronic device of claim 9 , wherein the first path selector:
outputs the inverted clock signal as the first internal clock signal and the clock signal as the third internal clock signal when the sign signal represents that the high level period of the clock signal is longer than the low level period of the clock signal; and outputs the clock signal as the first internal clock signal and the inverted clock signal as the third internal clock signal when the sign signal represents that the low level period of the clock signal is longer than the high level period of the clock signal.

11 - 12 . (canceled)

13 . The electronic device of claim 1 , wherein the second duty cycle correction circuit includes:
an integrator configured to generate a first voltage and a second voltage by performing the integration operation on a high level period of the first output clock signal and a low level period of the first output clock signal, respectively; a comparator configured to compare a magnitude of the first voltage with a magnitude of the second voltage to generate an up-down signal; a counter configured to generate a duty control code based on the up-down signal; and a duty adjust circuit configured to generate a temporary clock sig

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Won-Joo
• Shim Yong

Classifications

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title