Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof

Patent metadata

Field	Value
Publication number	US-9859337-B2
Application number	US-201615207042-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Feb 26, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate;
semiconductor local bit lines extending perpendicular to the top surface of the substrate; and
resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines,

wherein each of the semiconductor local bit lines comprises:
a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type; and
a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.

2. The three-dimensional memory device of claim 1 , further comprising a plurality of selector elements located at each level of the electrically conductive layers and contacting a respective resistive memory element.

3. The three-dimensional memory device of claim 2 , wherein:
a combination of a resistive memory element among the resistivity switching memory elements and a selector element among the plurality of selector elements is located at each level of the electrically conductive layers;
one of the resistive memory element and the selector element in the combination contacts a respective electrically conductive layer; and
another of the resistive memory element and the selector element in the combination contacts a respective drain region.

4. The three-dimensional memory device of claim 1 , wherein:
a predominant portion of each of the drain regions includes first-type electrical dopants at a dopant concentration greater than 1.0×10 19 /cm 3 ;
the semiconductor channel is intrinsic, undoped or includes second-type electrical dopants at a dopant concentration less than 1.0×10 18 /cm 3 ; and
the three-dimensional memory device further comprises global bit lines contacting a horizontal surface of a respective semiconductor channel and laterally extending along a second horizontal direction that is different from the first horizontal direction, wherein each of the global bit lines comprises a respective doped semiconductor rail having a doping of the first conductivity type at a dopant concentration greater than 1.0×10 19 /cm 3 .

5. The three-dimensional memory device of claim 1 , further comprising:
a gate dielectric continuously contacting a respective semiconductor channel from the level of the bottommost electrically conductive layer within the alternating stack to the level of the topmost electrically conductive layer within the alternating stack; and
a gate electrode laterally surrounded by a respective gate dielectric.

6. The three-dimensional memory device of claim 5 , wherein each combination of a global bit line comprising a doped semiconductor rail, the semiconductor channel, the drain region, the gate dielectric, and the gate electrode comprises a vertical field effect transistor.

7. The three-dimensional memory device of claim 6 , further comprising a plurality of selector elements located at each level of the electrically conductive layers and contacting a respective resistive memory element, wherein proximal sidewalls of the insulating layers are more proximal to the gate dielectric than the plurality of selector elements are to the gate dielectric.

8. The three-dimensional memory device of claim 7 , wherein the resistivity switching memory element is selected from a filament-forming dielectric material providing a reduced resistivity upon formation of conductive filaments, a vacancy modulated conductive oxide material providing an increased resistivity upon reduction of oxygen vacancy therein, or a phase change chalcogenide material.

9. The three-dimensional memory device of claim 5 , wherein each of the drain regions contacts respective portions of an outer sidewall of a respective gate dielectric.

10. The three-dimensional memory device of claim 5 , wherein portions of the drain regions of the semiconductor vertical bit lines are located in lateral recesses between adjacent insulating layers in the alternating stack.

11. The three-dimensional memory device of claim 10 , wherein an interface between a gate dielectric and a gate electrode generally extends vertically from the level of the bottommost electrically conductive layer to the level of the topmost electrically conductive layer, and has a laterally undulating profile, such that at least protruding portions of the semiconductor channel extend into lateral recesses in the gate dielectric and gate electrode.

12. The three-dimensional memory device of claim 5 , wherein an interface between a gate dielectric and a gate electrode extends along a vertical direction from the level of the bottommost electrically conductive layer to the level of the topmost electrically conductive layer.

13. The three-dimensional memory device of claim 1 , wherein the memory elements comprise a resistivity switching memory material selected from a filament-forming dielectric material providing a reduced resistivity upon formation of conductive filaments therein and a vacancy modulated conductive oxide material providing an increased resistivity upon reduction of oxygen vacancy therein.

14. The three-dimensional memory device of claim 1 , wherein each drain region extends above a horizontal surface including a bottom surface of an overlying insulating layer and extends below a horizontal surface including a top surface of an underlying insulating layer, and has a greater width at a level of a respective electrically conductive layer than at levels of the overlying insulating layer and the underlying insulating layer.

15. A method of making a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate;
patterning the alternating stack to form bit line cavities extending through the alternating stack;
laterally recessing sidewalls of the spacer material layers in the bit line cavities with respect to sidewalls of the insulating layers to form lateral recesses;
forming drain regions in the lateral recesses, each of the drain regions being a doped semiconductor region having a doping of a first conductivity type; and
forming a semiconductor channel layer in the bit line cavities over the drain regions and over the sidewalls of the insulating layers.

16. The method of claim 15 , wherein the spacer material layers are formed as, or are replaced with, electrically conductive layers which comprise word lines.

17. The method of claim 15 , further comprising expanding the drain regions by diffusing electrical dopants from the drain region as provided prior to formation of the semiconductor channel layer into adjacent portions of the semiconductor channel layer to convert the adjacent portions into additional doped semiconductor regions having a doping of the first conductivity type, wherein the expanded drain regions are spaced from one another by remaining portions of the semiconductor channel layer.

18. The method of claim 15 , further comprising forming a plurality of selector elements at each level of the spacer material layers, wherein each of the plurality of selector elements contacts a respective resistive memory element.

19. The method of claim 18 , wherein:
a comb

Assignees

• Sandisk Technologies Llc

Inventors

• Ratnam Perumal
• Bandyopadhyay Abhijit
• Petti Christopher J

Classifications

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L21/225

  Electricity · mapped topic