Trench MOSFET with self-aligned body contact with spacer

Patent metadata

Field	Value
Publication number	US-10930591-B2
Application number	US-201916375222-A
Country	US
Kind code	B2
Filing date	Apr 4, 2019
Priority date	Oct 19, 2015
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a plurality of gate trenches are formed into a semiconductor substrate. A body contact trench is formed into the semiconductor substrate in a mesa between the gate trenches. Spacers are deposited on sidewalls of the body contact trench. An ohmic body contact is implanted into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the implant. A body contact trench extension may be etched into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the etch, prior to the implant.

First claim

What is claimed is:

1. A method comprising:
forming a body contact trench into a semiconductor substrate;
depositing spacers on sidewalls of said body contact trench; and
implanting an ohmic body contact into said semiconductor substrate through said body contact trench utilizing said spacers to self-align said implanting.

2. The method of claim 1 further comprising:
etching a body contact trench extension into said semiconductor substrate through said body contact trench utilizing said spacers to self-align said etching.

3. The method of claim 2 wherein sidewalls of said body contact trench extension are more vertical than said sidewalls of said body contact trench.

4. The method of claim 2 wherein a width of said body contact trench extension is at least a width of said body contact trench.

5. The method of claim 1 further comprising:
removing said spacers.

6. The method of claim 5 wherein said removing comprises wet etching using hot phosphoric acid (H 3 PO 4 ).

7. The method of claim 5 wherein said removing comprises wet etching using BOE or dilute HF.

8. The method of claim 4 wherein a depth of said body contact trench is less than 0.5 μm.

9. A method comprising:
forming at least two parallel gate trenches into a semiconductor substrate;
forming a body contact trench into said semiconductor substrate in a mesa between said gate trenches;
depositing spacers on sidewalls of said body contact trench; and
implanting an ohmic body contact into said semiconductor substrate through said body contact trench utilizing said spacers to self-align said implanting,
wherein said ohmic body contact has a maximum horizontal extent that is less than the horizontal extent of the bottom of said body contact trench.

10. The method of claim 9 wherein said spacers are characterized as having a thickness in the range of 0.03 μm to 0.06 μm.

11. The method of claim 10 wherein a horizontal extent of said ohmic body contact implant differs from a lower width at the bottom of said body contact trench by about said thickness of said spacers from each side.

12. The semiconductor device of claim 9 wherein said spacers comprise nitride.

13. The semiconductor device of claim 9 wherein said spacers comprise chemical vapor deposition (CVD) oxide.

14. The semiconductor device of claim 9 further comprising a shield electrode, disposed below and electrically isolated from a gate electrode, in at least one of said gate trenches.

15. A method comprising:
forming at least two parallel gate trenches into a semiconductor substrate;
forming a body contact trench into said semiconductor substrate in a mesa between said gate trenches,
wherein said body contact trench characterized as having a substantially constant sidewall slope to a first depth below a primary surface of said semiconductor substrate;
depositing spacers on sidewalls of said body contact trench;
forming a body contact trench extension in said semiconductor substrate extending from the bottom of said body contact trench,
wherein a sidewall of said body contact trench extension is disjoint with said sidewall slope of said body contact trench; and
implanting an ohmic body contact implant beneath said body contact trench extension,
wherein a horizontal extent of said ohmic body contact implant is not greater than a width of said body contact trench at said first depth.

16. The method of claim 15 wherein said spacers are characterized as having a thickness in the range of 0.03 μm to 0.06 μm.

17. The method of claim 15 wherein a horizontal extent of said ohmic body contact implant differs from a lower width at the bottom of said body contact trench by about said thickness of said spacers from each side.

18. The semiconductor device of claim 15 wherein said spacers comprise nitride.

19. The semiconductor device of claim 15 wherein said spacers comprise chemical vapor deposition (CVD) oxide.

20. The semiconductor device of claim 15 further comprising a shield electrode, disposed below and electrically isolated from said gate electrode, in at least one of said gate trenches.

Assignees

• Vishay Siliconix
• Vishay Siliconix Llc

Inventors

• Guan Lingpeng
• Terrill Kyle
• Jo Seokjin

Classifications

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/605

  Source, drain, or gate electrodes for FETs comprising highly resistive materials · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title