Multilayer capacitor including liquid pocket

Patent metadata

Field	Value
Publication number	US-10930439-B2
Application number	US-202016815674-A
Country	US
Kind code	B2
Filing date	Mar 11, 2020
Priority date	Aug 1, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A multilayer capacitor includes a body in which a plurality of internal electrodes are stacked, including a ceramic sintered body; and external electrodes disposed on an external surface of the body and electrically connected to the internal electrodes. The ceramic sintered body includes a liquid pocket.

First claim

What is claimed is:

1. A multilayer capacitor comprising:
a body in which a plurality of internal electrodes are stacked, including a ceramic sintered body; and
external electrodes disposed on an external surface of the body and electrically connected to the internal electrodes,
wherein the ceramic sintered body includes a liquid pocket and a void,
wherein the void is embedded within the ceramic sintered body, and
wherein at least a portion of the liquid pocket is disposed at a grain boundary in the ceramic sintered body.

2. The multilayer capacitor of claim 1 , wherein the liquid pocket is disposed at a multiple grain boundary by at least three grains adjacent to each other among a plurality of grains included in the ceramic sintered body.

3. The multilayer capacitor of claim 1 , wherein among a plurality of grains included in the ceramic sintered body, a grain adjacent to the liquid pocket has a smaller size than that of a grain not adjacent to the liquid pocket.

4. The multilayer capacitor of claim 3 , wherein among the plurality of grains included in the ceramic sintered body, an average size of the grains adjacent to the liquid pocket is smaller than an average size of the grains that are not adjacent to the liquid pocket.

5. The multilayer capacitor of claim 1 , wherein the void has a larger size than that of the liquid pocket in terms of average size in a cross section.

6. The multilayer capacitor of claim 1 , wherein the void has a size of 0.1 to 10 μm based on a cross section.

7. The multilayer capacitor of claim 1 , wherein the ceramic sintered body is formed of a BT based ceramic material, and contains at least one of Si or Al ingredients as addition ingredients.

8. The multilayer capacitor of claim 1 , wherein an average interval between internal electrodes adjacent to each other among the plurality of internal electrodes is 0.4 μm or less.

9. The multilayer capacitor of claim 8 , wherein an average thickness of the plurality of internal electrodes is 0.4 μm or less.

10. The multilayer capacitor of claim 1 , wherein an average thickness of the plurality of internal electrodes is 0.4 μm or less.

11. The multilayer capacitor of claim 1 , wherein the liquid pocket is disposed in a dielectric layer separating adjacent internal electrodes.

12. A multilayer capacitor comprising:
a body in which a plurality of internal electrodes are stacked, including a ceramic sintered body; and
external electrodes disposed on an external surface of the body and electrically connected to the internal electrodes,
wherein the ceramic sintered body includes a grain, a liquid pocket and a void,
wherein the void has a size smaller than a size of the grain, and
wherein the void has a larger size than that of the liquid pocket in terms of average size in a cross section.

13. The multilayer capacitor of claim 12 , wherein an average interval between internal electrodes adjacent to each other among the plurality of internal electrodes is 0.4 μm or less.

14. The multilayer capacitor of claim 12 , wherein an average thickness of the plurality of internal electrodes is 0.4 μm or less.

15. A multilayer capacitor comprising:
a body in which a plurality of internal electrodes are stacked, including a ceramic sintered body; and
external electrodes disposed on an external surface of the body and electrically connected to the internal electrodes,
wherein the ceramic sintered body includes a grain boundary, a liquid pocket and a void,
wherein the void is disposed in the grain boundary, and
wherein the void has a size of 0.1 to 10 μm based on a cross section.

16. The multilayer capacitor of claim 15 , wherein an average interval between internal electrodes adjacent to each other among the plurality of internal electrodes is 0.4 μm or less.

17. The multilayer capacitor of claim 15 , wherein an average thickness of the plurality of internal electrodes is 0.4 μm or less.

Assignees

• Samsung Electro Mech

Inventors

• Park Byung Hyun

Classifications

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/1227 Primary

  based on alkaline earth titanates · CPC title

• H01G4/1209 Primary

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title