PCIE lane aggregation over a high speed link

Patent metadata

Field	Value
Publication number	US-10929325-B2
Application number	US-202016738984-A
Country	US
Kind code	B2
Filing date	Jan 9, 2020
Priority date	Aug 9, 2013
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.

First claim

What is claimed is:

1. A computer network system comprising:
an I/O appliance having a downstream silicon photonics device provided on each of a plurality of optical ports numbered from 1 to N; and
a plurality of server devices coupled to the I/O appliance, each of the server devices comprising a PCIe (Peripheral Component Interconnect Express) interface, and an upstream silicon photonics device coupled to each of the plurality of server devices and aggregating each of the PCIe interfaces.

2. The system of claim 1 further comprising a twisted pair configured between the PCIe interfaces and the upstream silicon photonics device.

3. The system of claim 1 wherein the downstream silicon photonics device and the upstream silicon photonics device are configured in a 1-to-1 mapping.

4. The system of claim 1 wherein a high-speed link is configured between the downstream silicon photonics device and the upstream silicon photonics device.

5. The system of claim 4 further comprising a pair of optical convertors coupled by an optical fiber configured between the upstream silicon photonics device and the downstream silicon photonics device.

6. A computer network system comprising:
a router coupled to a network source;
a plurality of core switches coupled to the router;
a plurality of aggregator switches coupled to each of the plurality of core switches; and
a plurality of rack modules coupled to each of the plurality of aggregator switches, wherein each of the plurality of rack modules comprises:
an I/O appliance having a downstream aggregator module provided on each of a plurality of optical ports numbered from 1 to N; and
a plurality of server devices coupled to the I/O appliance, each of the server devices having a PCIe (Peripheral Component Interconnect Express) interface, and an upstream aggregator module coupled to the plurality of server devices and aggregating each of the PCIe interfaces.

7. The system of claim 6 wherein the downstream aggregator module is coupled to one or more PCIe EP (End Point) modules; and wherein the downstream aggregator module and the one or more PCIe EP modules are integrated on a silicon material.

8. The system of claim 6 wherein the downstream aggregator module and the upstream aggregator module are configured in a 1-to-1 mapping.

9. The system of claim 6 wherein a high-speed link is configured between the downstream aggregator module and the upstream aggregator module.

10. The system of claim 9 further comprising a pair of optical convertors coupled by an optical fiber configured between the upstream aggregator module and the downstream aggregator module; and wherein the computer network system is configured in a leaf-spine architecture.

11. A method of operating a computer network system having an I/O appliance, a plurality of server devices coupled to the I/O appliance, and an upstream silicon photonics device coupled to each of the plurality of server devices; the method comprising:
receiving, by a plurality of optical ports of the I/O appliance numbered from 1 to N, a data stream;
aggregating, by a downstream silicon photonics device of the I/O appliance provided on each of the plurality of optical ports, the data stream;
processing, by a Peripheral Component Interconnect Express (PCIe) interface of each server device, the data stream; and
aggregating, each of the PCIe interfaces to aggregate the data stream.

12. The method of claim 11 , wherein aggregating each of the PCIe interfaces includes aggregating via a twisted pair configuration between the PCIe interfaces and the upstream silicon photonics device.

13. The method of claim 11 , wherein the downstream silicon photonics device and the upstream silicon photonics device are configured in a 1-to-1 mapping.

14. The method of claim 11 further comprising communicating, by a high-speed link configured between the downstream silicon photonics device and the upstream silicon photonics device, the data stream.

15. The method of claim 14 further comprising converting, by a pair of optical converters coupled by an optical fiber configured between the upstream silicon photonics device and the downstream silicon photonics device, the data stream.

Assignees

• Inphi Corp

Inventors

• Krishnan Sreenivas
• Saxena Nirmal Raj

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• H04B10/27

  Arrangements for networking · CPC title

• H04L12/64

  Hybrid switching systems · CPC title

• H04L12/66

  Arrangements for connecting between networks having differing types of switching systems, e.g. gateways · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title